AD9484 Analog Devices, AD9484 Datasheet - Page 15

• Manufacturer Part Number: AD9484
• Description: 8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9484

• Resolution (bits): 8bit
• # Chan: 1
• Sample Rate: 500MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.5 V p-p,Bip 0.75V
• Adc Architecture: Pipelined
• Pkg Type: CSP

CLOCK INPUT CONSIDERATIONS
For optimum performance, drive the AD9484 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased at ~0.9 V
internally and require no additional bias. If the clock signal is
dc-coupled, then the common-mode voltage should remain
within a range of 0.9 V.
Figure 33 shows one preferred method for clocking the AD9484.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9484 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9484 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
ANALOG INPUT
ANALOG INPUT
1
1
50Ω RESISTORS ARE OPTIONAL.
50Ω RESISTORS ARE OPTIONAL.
CLOCK
CLOCK
CLOCK
CLOCK
INPUT
INPUT
INPUT
INPUT
C
D
50Ω
50Ω
Figure 30. Differential Input Configuration Using the AD8352
0.1µF
0.1µF
R
1
1
D
0Ω
0Ω
Figure 32. Differential LVDS Sample Clock
R
Figure 31. Differential PECL Sample Clock
0.1µF
0.1µF
0.1µF
0.1µF
50Ω
50Ω
G
16
1
2
3
4
5
1
1
CLK
CLK
CLK
CLK
PECL DRIVER
LVDS DRIVER
V
AD8352
CC
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
Rev. A | Page 15 of 24
8, 13
14
0.1µF
0.1µF
240Ω
11
10
0.1µF
0.1µF
If a low jitter clock is available, another option is to ac couple a
differential PECL signal to the sample clock input pins, as
shown in Figure 31. The AD9510/AD9511/AD9512/AD9513/
AD9514/AD9515
performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate,
and bypass the CLK− pin to ground with a 0.1 μF capacitor in
parallel with a 39 kΩ resistor (see Figure 34).
240Ω
CLOCK
INPUT
200Ω
200Ω
100Ω
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
Figure 33. Transformer-Coupled Differential Clock
0.1µF
R
R
C
50Ω
0.1µF
CLK+
CLK–
CLK+
CLK–
AD9484
AD9484
family of clock drivers offers excellent jitter
ADC
ADC
100Ω
AD9484
VIN+
VIN– CML
ADT1–1WT, 1:1Z
MINI-CIRCUITS
XFMR
0.1µF
0.1µF
0.1µF
SCHOTTKY
HSM2812
DIODES:
CLK+
CLK–
AD9484
ADC
AD9484