AD7985 Analog Devices, AD7985 Datasheet - Page 24

• Manufacturer Part Number: AD7985
• Description: 16-Bit, 2.5 MSPS PulSAR 11 mW ADC in QFN
• Manufacturer: Analog Devices

Specifications of AD7985

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 2.5MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP

AD7985
CHAIN MODE WITH BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7985 devices
on a 3-wire serial interface while providing a busy indicator. It
is available only in normal conversion mode (TURBO is low).
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications
or for systems with a limited interfacing capacity. Data readback
is analogous to clocking a shift register. A connection diagram
example using three AD7985 devices is shown in Figure 36, and
the corresponding timing is given in Figure 37.
When SDI and CNV are low, SDO is driven low. With SCK high,
a rising edge on CNV initiates a conversion, selects chain mode,
and enables the busy indicator feature. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback.
TURBO = 0
ACQUISITION
SDO
SDO
CNV = SDI
t
HSCKCNV
SCK
A
B
= SDI
= SDI
SDO
A
B
C
C
CONVERSION
t
t
DSDOSDI
t
SSCKCNV
t
SDI
CONV
DSDOSDI
t
EN
AD7985
CNV
SCK
A
t
t
t
SSDISCK
HSDO
DSDO
1
TURBO
D
D
D
C
SDO
A
B
2
15 D
15 D
15 D
Figure 37. Chain Mode with Busy Indicator Serial Interface Timing
Figure 36. Chain Mode with Busy Indicator Connection Diagram
C
A
B
3
14 D
14 D
14 D
t
SCKH
C
A
B
4
t
SDI
HSDISCK
13
13
13
AD7985
15
t
SCK
CNV
SCK
B
D
D
D
16
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C
B
A
1
1
1
TURBO
t
SCKL
SDO
D
D
D
17
C
A
B
0
0
0 D
D
ACQUISITION
18
B
A
t
15 D
15 D
CYC
When all ADCs in the chain have completed their conversions, the
SDO pin of the ADC closest to the digital host (see the AD7985
ADC labeled C in Figure 36) is driven high. This transition on
SDO can be used as a busy indicator to trigger the data read-
back controlled by the digital host. The AD7985 then enters the
acquisition phase and powers down. The data bits stored in the
internal shift register are clocked out, MSB first, by subsequent SCK
falling edges. For each ADC, SDI feeds the input of the internal
shift register and is clocked by the SCK falling edge. Each ADC
in the chain outputs its data MSB first, and 16 × N + 1 clocks
are required to read back the N ADCs. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate and consequently more
AD7985 devices in the chain, provided that the digital host has
an acceptable hold time.
SDI
19
B
A
t
14
14
ACQ
AD7985
31
CNV
SCK
C
D
D
32
B
TURBO
A
1
1
SDO
D
D
33
B
A
0 D
0
34
A
15
D
CONVERT
DATA IN
CLK
IRQ
35
A
DIGITAL HOST
14
47
t
DSDOSDI
D
48
t
A
DSDOSDI
t
1
DSDOSDI
D
49
A
0