AD9649 Analog Devices, AD9649 Datasheet - Page 21

• Manufacturer Part Number: AD9649
• Description: 14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9649

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive
to clock duty cycle. Commonly, a 50% duty cycle clock with ±5%
tolerance is required to maintain optimum dynamic performance,
as shown in Figure 52.
Jitter on the rising edge of the clock input can also impact dynamic
performance and should be minimized, as discussed in the Jitter
Considerations section of this datasheet.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNR
jitter (t
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 53.
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9649.
To avoid modulating the clock signal with digital noise, keep power
SNR
80
75
70
65
60
55
50
45
80
75
70
65
60
55
50
45
40
JRMS
10
1
HF
) can be calculated by
= −10 log[(2π × f
Figure 53. SNR vs. Input Frequency and Jitter
20
Figure 52. SNR vs. Clock Duty Cycle
LF
) at a given input frequency (f
30
POSITIVE DUTY CYCLE (%)
10
FREQUENCY (MHz)
INPUT
40
× t
50
JRMS
)
100
2
+ 10
60
3.0ps
(
−
SNR
0.05ps
0.2ps
0.5ps
1.0ps
1.5ps
2.0ps
2.5ps
70
INPUT
LF
/
10
) due to
)
1k
80
]
Rev. 0 | Page 21 of 32
supplies for clock drivers separate from the ADC output driver
supplies. Low jitter, crystal-controlled oscillators make the best
clock sources. If the clock is generated from another type of source
(by gating, dividing, or another method), it should be retimed by
the original clock at the last step.
For more information, see the AN-501 Application Note and the
AN-756 Application Note, which are available on www.analog.com.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 54, the analog core power dissipated by the
AD9649 is proportional to its sample rate. The digital power dis-
sipation of the CMOS outputs are determined primarily by the
strength of the digital drivers and the load on each output bit.
The maximum DRVDD current (I
where N is the number of output bits (15, in the case of the
AD9649).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of f
lished by the average number of output bits that are switching,
which is determined by the sample rate and the characteristics
of the analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 54 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
In SPI mode, the AD9649 can be placed in power-down mode
directly via the SPI port or by using the programmable external
MODE pin. In non-SPI mode, power-down is achieved by assert-
ing the PDWN pin high. In this state, the ADC typically dissipates
500 μW. During power-down, the output drivers are placed in a
high impedance state. Asserting the PDWN pin (or the MODE pin
in SPI mode) low returns the AD9649 to normal operating mode.
Note that PDWN is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
I
DRVDD
85
80
75
70
65
60
55
50
45
40
35
10
= V
AD9649-20
CLK
Figure 54. Analog Core Power vs. Clock Rate
DRVDD
20
/2. In practice, the DRVDD current is estab-
× C
30
LOAD
CLOCK RATE (MSPS)
AD9649-40
× f
40
CLK
DRVDD
× N
AD9649-65
50
) can be calculated as
60
AD9649-80
70
AD9649
80