AD9230-11 Analog Devices, AD9230-11 Datasheet - Page 16

• Manufacturer Part Number: AD9230-11
• Description: 11-Bit, 200 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9230-11

• Resolution (bits): 11bit
• # Chan: 1
• Sample Rate: 200MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Uni
• Ain Range: 1.25 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9230-11
THEORY OF OPERATION
The AD9230-11 architecture consists of a front-end sample-
and-hold amplifier (SHA) followed by a pipelined switched
capacitor ADC. The quantized outputs from each stage are
combined into a final 11-bit result in the digital correction
logic. The pipelined architecture permits the first stage to
operate on a new input sample, while the remaining stages operate
on preceding samples. Sampling occurs on the rising edge of the
clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a buffered differential SHA that can
be ac- or dc-coupled. The output staging block aligns the data,
carries out the error correction, and passes the data to the out-
put buffers. The output buffers are powered from a separate
supply, allowing adjustment of the output voltage swing. During
power-down, the output buffers go into a high impedance state.
ANALOG INPUT AND VOLTAGE REFERENCE
The analog input to the AD9230-11 is a differential buffer. For
best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched such that common-mode
settling errors are symmetrical. The analog input is optimized
to provide superior wideband performance and requires that
the analog inputs be driven differentially. SNR and SINAD
performance degrades significantly if the analog input is driven
with a single-ended signal.
A wideband transformer, such as Mini-Circuits® ADT1-1WT, can
provide the differential analog inputs for applications that require a
single-ended-to-differential conversion. Both analog inputs are self-
biased by an on-chip resistor divider to a nominal 1.4 V. An
internal differential voltage reference creates positive and negative
reference voltages that define the 1.25 V p-p fixed span of the ADC
core. This internal voltage reference can be adjusted by means of
SPI control. See the Configuration Using the SPI section.
ANALOG INPUT
ANALOG INPUT
C
D
Figure 23. Differential Input Configuration Using the AD8352
0.1µF
0.1µF
R
D
0Ω
0Ω
R
G
16
1
2
3
4
5
V
AD8352
CC
Rev. 0 | Page 16 of 28
8, 13
14
0.1µF
0.1µF
11
10
0.1µF
0.1µF
Differential Input Configurations
Optimum performance is achieved while driving the AD9230-11
in a differential input configuration. For baseband applications,
the
and a flexible interface to the ADC. The output common-mode
voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers may not be adequate to achieve the
true performance of the AD9230-11. This is especially true in IF
undersampling applications where frequencies in the 70 MHz to
100 MHz range are being sampled. For these applications, differen-
tial transformer coupling is the recommended input configuration.
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies below a
few megahertz and excessive signal power can also cause core
saturation, leading to distortion. In any configuration, the value of
the shunt capacitor, C, is dependent on the input frequency and
may need to be reduced or removed.
As an alternative to using a transformer-coupled input at frequen-
cies in the second Nyquist zone, the
be used (see Figure 23).
1V p-p
AD8138
200Ω
200Ω
Figure 21. Differential Input Configuration Using the AD8138
Figure 22. Differential Transformer—Coupled Configuration
1.25V p-p
0.1µF
R
R
0.1µF
C
49.9Ω
differential driver provides excellent performance
AD9230-11
499Ω
523Ω
50Ω
VIN+
VIN– CML
0.1µF
AD8138
499Ω
499Ω
15Ω
15Ω
2pF
AD8352
33Ω
33Ω
20pF
AD9230-11
VIN+
VIN–
differential driver can
AD9230-11
VIN+
VIN–
AVDD
CML