AD9230-11 Analog Devices, AD9230-11 Datasheet - Page 17

• Manufacturer Part Number: AD9230-11
• Description: 11-Bit, 200 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9230-11

• Resolution (bits): 11bit
• # Chan: 1
• Sample Rate: 200MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Uni
• Ain Range: 1.25 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9230-11 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ pin and the
CLK− pin via a transformer or capacitors. These pins are biased
internally and require no additional bias.
Figure 24 shows a preferred method for clocking the AD9230-11.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9230-11 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9230-11 and preserves the
fast rise and fall times of the signal, which are critical to low
jitter performance.
If a low jitter clock is available, another option is to ac couple
a differential PECL signal to the sample clock input pins as
shown in Figure 25. The AD9510/AD9511/AD9512/AD9513/
AD9514/AD9515
performance.
*50Ω RESISTORS ARE OPTIONAL.
CLOCK
CLOCK
CLOCK
CLOCK
*50Ω RESISTORS ARE OPTIONAL.
CLOCK
INPUT
INPUT
INPUT
INPUT
INPUT
50Ω*
50Ω*
Figure 24. Transformer-Coupled Differential Clock
50Ω
0.1µF
Figure 26. Differential LVDS Sample Clock
Figure 25. Differential PECL Sample Clock
50Ω*
0.1µF
0.1µF
0.1µF
0.1µF
50Ω*
family of clock drivers offers excellent jitter
100Ω
ADT1–1WT, 1:1Z
CLK
CLK
MINI-CIRCUITS
CLK
CLK
LVDS DRIVER
PECL DRIVER
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
XFMR
0.1µF
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
240Ω
0.1µF
0.1µF
SCHOTTKY
HSM2812
DIODES:
240Ω
100Ω
0.1µF
0.1µF
100Ω
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
AD9230-11
AD9230-11
CLK+
CLK–
AD9230-11
ADC
ADC
ADC
Rev. 0 | Page 17 of 28
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 27). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V (as shown in
Figure 28), making the selection of the drive logic voltage very
flexible.
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9230-11 contains a duty cycle stabilizer
(DCS) that retimes the nonsampling edge, providing an internal
clock signal with a nominal 50% duty cycle. This allows a wide
range of clock input duty cycles without affecting the perform-
ance of the AD9230-11. When the DCS is on, noise and distortion
performance are nearly flat for a wide range of duty cycles.
However, some applications may require the DCS function to
be off. If so, keep in mind that the dynamic range performance can
be affected when operated in this mode. See the Configuration
Using the SPI section for more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
CLOCK
*50Ω RESISTOR IS OPTIONAL.
INPUT
*50Ω RESISTOR IS OPTIONAL.
CLOCK
INPUT
0.1µF
50Ω*
0.1µF
Figure 27. Single-Ended 1.8 V CMOS Sample Clock
Figure 28. Single-Ended 3.3 V CMOS Sample Clock
50Ω*
0.1µF
0.1µF
CLK
CLK
CLK
CLK
CMOS DRIVER
CMOS DRIVER
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
OPTIONAL
OPTIONAL
100Ω
100Ω
39kΩ
0.1µF
0.1µF
0.1µF
AD9230-11
AD9230-11
CLK+
CLK–
CLK+
CLK–
AD9230-11
ADC
ADC