AD7764 Analog Devices, AD7764 Datasheet - Page 16

• Manufacturer Part Number: AD7764
• Description: 24-Bit, 312 kSPS, 109 dB Sigma Delta ADC with On-Chip Buffers and Serial Interface
• Manufacturer: Analog Devices

Specifications of AD7764

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 40MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: 6.5 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7764
THEORY OF OPERATION
The AD7764 features an on-chip fully differential amplifier to
feed the Σ-Δ modulator pins, an on-chip reference buffer, and
a FIR filter block to perform the required digital filtering of the
Σ-Δ modulator output. Using this Σ-Δ conversion technique
with the added digital filtering, the analog input is converted to
an equivalent digital word.
Σ-Δ MODULATION AND DIGITAL FILTERING
The input waveform applied to the modulator is sampled, and
an equivalent digital word is output to the digital filter at a rate
equal to ICLK. By employing oversampling, the quantization
noise is spread across a wide bandwidth from 0 to f
means that the noise energy contained in the signal band of
interest is reduced (see Figure 29). To further reduce the
quantization noise, a high-order modulator is employed to
shape the noise spectrum so that most of the noise energy is
shifted out of the signal band (see Figure 30).
Table 6. Configuration with Default Filter
ICLK
Frequency
20 MHz
20 MHz
20 MHz
12.288 MHz
12.288 MHz
12.288 MHz
BAND OF INTEREST
BAND OF INTEREST
BAND OF INTEREST
Figure 31. Σ-Δ ADC, Digital Filter Cutoff Frequency
Figure 29. Σ-Δ ADC, Quantization Noise
Figure 30. Σ-Δ ADC, Noise Shaping
Decimation
Rate
64×
128×
256×
64×
128×
256×
DIGITAL FILTER CUTOFF FREQUENCY
QUANTIZATION NOISE
NOISE SHAPING
Data State
Fully filtered
Fully filtered
Fully filtered
Fully filtered
Fully filtered
Fully filtered
f
f
f
ICLK
ICLK
ICLK
Computation
Delay
2.25 µs
3.1 µs
4.65 µs
3.66 µs
5.05 µs
7.57 µs
/2
/2
/2
ICLK
. This
Rev. A | Page 16 of 32
Filter Delay
87.6 µs
174 µs
346.8 µs
142.6 µs
283.2 µs
564.5 µs
The digital filtering that follows the modulator removes the
large out-of-band quantization noise (see Figure 31) while also
reducing the data rate from f
f
decimation rate used.
The AD7764 employs three FIR filters in series. By using
different combinations of decimation ratios, data can be
obtained from the AD7764 at three data rates.
The first filter receives data from the modulator at ICLK MHz
where it is decimated 4× to output data at (ICLK/4) MHz. The
second filter allows the decimation rate to be chosen from
8× to 32×.
The third filter has a fixed decimation rate of 2×. Table 6 shows
some characteristics of the digital filtering where ICLK =
MCLK/2. The group delay of the filter is defined to be the delay
to the center of the impulse response and is equal to the compu-
tation plus the filter delays. The delay until valid data is available
(the FILTER-SETTLE status bit is set) is approximately twice
the filter delay plus the computation delay. This is listed in
terms of MCLK periods in Table 6.
ICLK
/64 or less at the output of the filter, depending on the
–100
–120
–140
–160
–20
–40
–60
–80
0
Figure 32. Filter Frequency Response (312.5 kHz ODR)
0
SYNC
FILTER-SETTLE
7122 × t
14217 × t
27895 × t
7122 × t
14217 × t
27895 × t
to
50
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
100
FREQUENCY (kHz)
ICLK
Pass-Band
Bandwidth
125 kHz
62.5 kHz
31.25 kHz
76.8 kHz
38.4 kHz
19.2 kHz
150
at the input of the filter to
PASS-BAND RIPPLE = 0.05dB
–0.1dB FREQUENCY = 125.1kHz
–3dB FREQUENCY = 128kHz
STOP BAND = 156.25kHz
200
Output Data Rate
(ODR)
312.5 kHz
156.25 kHz
78.125 kHz
192 kHz
96 kHz
48 kHz
250
300