AD7764 Analog Devices, AD7764 Datasheet - Page 24

• Manufacturer Part Number: AD7764
• Description: 24-Bit, 312 kSPS, 109 dB Sigma Delta ADC with On-Chip Buffers and Serial Interface
• Manufacturer: Analog Devices

Specifications of AD7764

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 40MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: 6.5 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7764
DAISY CHAINING
Daisy chaining allows numerous devices to use the same digital
interface lines. This feature is especially useful for reducing
component count and wiring connections, such as in isolated
multiconverter applications or for systems with a limited
interfacing capacity. Data readback is analogous to clocking a
shift register. When daisy chaining is used, all devices in the
chain must operate in a common power mode and at a common
decimation rate.
The block diagram in Figure 45 shows how to connect devices
to achieve daisy-chain functionality. Figure 45 shows four
AD7764 devices daisy-chained together with a common
MCLK signal applied. This can work in decimate 128× or
decimate 256× mode only.
READING DATA IN DAISY-CHAIN MODE
Referring to Figure 45, note that the SDO line of AD7764 (A)
provides the output data from the chain of AD7764 converters.
Also, note that for the last device in the chain, AD7764 (D), the
SDI pin is connected to ground. All of the devices in the chain
must use common MCLK and SYNC
To enable the daisy-chain conversion process, apply a common
SYNC
After a
time must pass before the FILTER-SETTLE bit is asserted,
indicating valid conversion data at the output of the chain of
devices. As shown in Figure 46, the first conversion result is
SDI (A) = SDO (B)
SDI (B) = SDO (C)
SDI (C) = SDO (D)
pulse to all devices (see the Synchronization section).
SDO (A)
FSO (A)
SYNC pulse is applied to all devices, the filter settling
SCO
MCLK
SYNC
FSI
32-BIT OUTPUT
AD7764 (B)
AD7764 (C)
AD7764 (D)
32 ×
AD7764 (A)
Figure 45. Daisy Chaining Four Devices in Decimate 128× Mode Using a 40 MHz MCLK Signal
t
SCO
FSI
SDI
SYNC
AD7764
MCLK
(D)
signals.
SDO
Figure 46. Daisy-Chain Mode, Data Read Timing Diagram
32-BIT OUTPUT
(for the Daisy-Chain Configuration Shown in Figure 45)
AD7764 (C)
AD7764 (D)
32 ×
AD7764 (B)
t
SCO
FSI
SDI
SYNC
AD7764
MCLK
(C)
Rev. A | Page 24 of 32
SDO
32-BIT OUTPUT
AD7764 (D)
32 ×
AD7764 (C)
t
SCO
output from the device labeled AD7764 (A). This 32-bit
conversion result is then followed by the conversion results
from the AD7764 (B), AD7764 (C), and AD7764 (D) devices
with all conversion results output in an MSB-first sequence.
The signals output from the daisy chain are the stream of
conversion results from the SDO pin of AD7764 (A) and the
FSO signal output by the first device in the chain, AD7764 (A).
The falling edge of FSO signals the MSB of the first conversion
output in the chain. FSO
clock periods needed to output the AD7764 (A) result and then
goes logic high during the output of the conversion results from
the AD7764 (B), AD7764 (C), and AD7764 (D devices.
The maximum number of devices that can be daisy-chained is
dependent on the decimation rate selected. Calculate the
maximum number of devices that can be daisy-chained by
simply dividing the chosen decimation rate by 32 (the number
of bits that must be clocked out for each conversion).
provides the maximum number of chained devices for each
decimation rate.
Table 12. Maximum Chain Length for all Decimation Rates
Decimation Rate
256×
128×
64×
FSI
SDI
SYNC
AD7764
MCLK
(B)
32-BIT OUTPUT
32 ×
AD7764 (D)
SDO
t
SCO
stays logic low throughout the 32 SCO
FSI
SDI
SYNC
32-BIT OUTPUT
AD7764 (B)
AD7764 (C)
AD7764 (D)
Maximum Chain Length
8
4
2
AD7764
AD7764 (A)
MCLK
(A)
SDO
FSO
32-BIT OUTPUT
AD7764 (C)
AD7764 (D)
AD7764 (B)
Table 12