AD7764 Analog Devices, AD7764 Datasheet - Page 9

• Manufacturer Part Number: AD7764
• Description: 24-Bit, 312 kSPS, 109 dB Sigma Delta ADC with On-Chip Buffers and Serial Interface
• Manufacturer: Analog Devices

Specifications of AD7764

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 40MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: 6.5 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
24
7 and 21
28
25
17
22
23
20
8
26
27
1
2
3
4
5
6
9
10
11
12
13
Mnemonic
AV
AV
AV
AV
DV
R
AGND1
AGND2
AGND3
REFGND
V
V
V
V
V
V
V
OVERRANGE
SCO
FSO
SDO
SDI
BIAS
REF
IN
OUT
IN
OUT
IN
IN
DD
DD
DD
DD
A−
A+
−
+
DD
+
A+
A−
1
2
3
4
Description
2.5 V Power Supply for Modulator. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF capacitor.
5 V Power Supply. Pin 7 should be decoupled to AGND3 (Pin 8) with a 100 nF capacitor. Pin 21 should be
decoupled to AGND1 (Pin 23) with a 100 nF capacitor.
3.3 V to 5 V Power Supply for Differential Amplifier. This pin should be decoupled to the ground plane with
a 100 nF capacitor.
3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF
capacitor.
2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to the ground plane with
a 100 nF capacitor.
Bias Current Setting Pin. This pin must be decoupled to the ground plane. For more details, see the
Bias Resistor Selection section.
Power Supply Ground for Analog Circuitry.
Power Supply Ground for Analog Circuitry.
Power Supply Ground for Analog Circuitry.
Reference Ground. Ground connection for the reference voltage.
Reference Input.
Negative Input to Differential Amplifier.
Positive Output from Differential Amplifier.
Positive Input to Differential Amplifier.
Negative Output from Differential Amplifier.
Negative Input to the Modulator.
Positive Input to the Modulator.
Overrange Pin. This pin outputs a logic high to indicate that the user has applied an analog input that is
approaching the limit of the analog input to the modulator.
Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of this clock is equal
to ICLK. See the Clocking the AD7764 section for further details.
Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide.
Serial Data Out. Data and status are output on this pin during each serial transfer. Each bit is clocked out on an
SCO rising edge and is valid on the falling edge. See the AD7764 Interface section for further details.
Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI event is latched.
Thirty-two bits are required for each write; the first 16-bit word contains the device and register address, and
the second word contains the data. See the AD7764 Interface section for further details.
OVERRANGE
V
V
AGND3
OUT
AV
OUT
V
V
IN
IN
V
SCO
SDO
V
FSO
DD
SDI
FSI
IN
IN
A–
A+
A+
A–
+
–
2
Figure 5. Pin Configuration
10
11
12
13
14
1
3
4
5
6
2
7
8
9
(Not to Scale)
Rev. A | Page 9 of 32
AD7764
TOP VIEW
16
15
28
27
26
25
24
23
22
21
20
19
18
17
AV
V
REFGND
AV
AV
AGND1
R
AV
AGND2
MCLK
DEC_RATE
DV
RESET/PWRDWN
SYNC
REF
BIAS
DD
DD
DD
DD
DD
+
3
4
1
2
AD7764