AD7621 Analog Devices, AD7621 Datasheet - Page 10

• Manufacturer Part Number: AD7621
• Description: 16-Bit, 2 LSB INL, 3 MSPS PulSAR® ADC
• Manufacturer: Analog Devices

Specifications of AD7621

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 3MSPS
• Interface: Byte,Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7621
Pin No.
32
33
34
35
36
37
38
39
43
45
46
47
48
1
AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
CS
PD
CNVST
AGND
REF
REFGND
IN−
IN+
TEMP
REFBUFIN
PDREF
PDBUF
Mnemonic
RESET
Type
DI
DI
DI
DI
P
AI/O
AI
AI
AI
AO
AI/O
DI
DI
1
Description
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock in slave serial mode.
Reset Input. When high, reset the AD7621. Current conversion if any is aborted. Falling edge of RESET
enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface section. If
not used, this pin can be tied to DGND.
Power-Down Input. When high, power down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed.
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion.
Analog Power Ground Pin.
Reference Output/Input.
Reference Input Analog Ground.
Differential Negative Analog Input.
Differential Positive Analog Input.
Temperature Sensor Analog Output.
Internal Reference Output/Reference Buffer Input.
Internal Reference Power-Down Input.
Internal Reference Buffer Power-Down Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin.
When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally
supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal
reference and buffer. Refer to the Voltage Reference Input section.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V
(typical) bandgap output on this pin, which needs external decoupling. The internal fixed gain
reference buffer uses this to produce 2.048V on the REF pin.
When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high),
applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section.
When low, the internal reference is enabled.
When high, the internal reference is powered down and an external reference must been used.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.
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