AD7450A Analog Devices, AD7450A Datasheet - Page 22

• Manufacturer Part Number: AD7450A
• Description: Differential Input, 1 MSPS, 12- (AD7450A) & 10-Bit (AD7440) ADCs
• Manufacturer: Analog Devices

Specifications of AD7450A

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

AD7440/AD7450A
Timing Example 1
Having F
cycle time of
A cycle consists of
Therefore, if t
This 296 ns satisfies the requirement of 290 ns for t
From Figure 40, t
where t
satisfying the minimum requirement of 60 ns.
1/Throughput = 1/1,000,000 = 1 μs
t
10 ns + 12.5(1/18 MHz) + t
t
2.5(1/F
2
ACQ
+ 12.5(1/F
8
= 35 ns. This allows a value of 122 ns for t
SCLK
= 296 ns
SCLK
= 18 MHz and a throughput rate of 1 MSPS gives a
2
= 10 ns
) + t
SCLK
ACQ
8
) + t
comprises
+ t
QUIET
ACQ
= 1 μs
ACQ
= 1 μs
QUIET
ACQ
.
,
Rev. C | Page 22 of 28
Timing Example 2
Having F
cycle time of
A cycle consists of
Therefore, if t
This 664 ns satisfies the requirement of 290 ns for t
From Figure 40, t
where t
satisfying the minimum requirement of 60 ns.
As in this example and with other slower clock values, the signal
may already be acquired before the conversion is complete, but
it is still necessary to leave 60 ns minimum t
conversions. In Timing Example 2, the signal should be fully
acquired at approximately Point C in Figure 40.
1/Throughput = 1/315,000 = 3.174 μs
t
10 ns + 12.5(1/5 MHz) + t
t
2.5(1/F
2
ACQ
+ 12.5(1/F
8
= 35 ns. This allows a value of 129 ns for t
SCLK
= 664 ns
SCLK
= 5 MHz and a throughput rate of 315 kSPS gives a
2
is 10 ns
) + t
SCLK
ACQ
8
) + t
+ t
comprises
QUIET
ACQ
= 3.174 μs
ACQ
= 3.174 μs
QUIET
between
QUIET,
ACQ
.