AD7450A Analog Devices, AD7450A Datasheet - Page 9

• Manufacturer Part Number: AD7450A
• Description: Differential Input, 1 MSPS, 12- (AD7450A) & 10-Bit (AD7440) ADCs
• Manufacturer: Analog Devices

Specifications of AD7450A

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Mnemonic
V
V
V
GND
CS
SDATA
SCLK
V
REF
IN+
IN–
DD
Figure 5. Pin Configuration for 8-Lead SOT-23
Function
Reference Input for the AD7440/AD7450A. An external reference must be applied to this input. For a 5 V power supply, the
reference is 2.5 V (±1%) for specified performance. For a 3 V power supply, the reference is 2 V (±1%) for specified
performance. This pin should be decoupled to GND with a capacitor of at least 0.1 μF. See the Reference section for more
details.
Positive Terminal for Differential Analog Input.
Negative Terminal for Differential Analog Input.
Analog Ground. Ground reference point for all circuitry on the AD7440/AD7450A. All analog input signals and any external
reference signal should be referred to this GND voltage.
Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7440/AD7450A
and framing the serial data transfer.
Serial Data. Logic output. The conversion result from the AD7440/AD7450A is provided on this output as a serial data stream.
The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7450A consists of four leading zeros
followed by the 12 bits of conversion data, which are provided MSB first; the data stream of the AD7440 consists of four
leading zeros, followed by the 10 bits of conversion data, followed by two trailing zeros. In both cases, the output coding is
twos complement.
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the
clock source for the conversion process.
Power Supply Input. V
a 10 μF tantalum capacitor in parallel.
SDATA
SCLK
V
CS
DD
1
2
3
4
(Not to Scale)
AD7450A
AD7440/
TOP VIEW
DD
is 3 V (+20%/–10%) or 5 V (±5%). This supply should be decoupled to GND with a 0.1 μF capacitor and
8
7
6
5
V
V
V
GND
REF
IN+
IN–
Rev. C | Page 9 of 28
Figure 6. Pin Configuration for 8-Lead MSOP
V
GND
V
V
REF
IN+
IN–
1
2
3
4
(Not to Scale)
AD7450A
AD7440/
TOP VIEW
AD7440/AD7450A
8
7
6
5
V
SCLK
SDATA
CS
DD