AD9878 Analog Devices, AD9878 Datasheet - Page 15

• Manufacturer Part Number: AD9878
• Description: Low Cost, 3.3 V, CMOS Mixed Signal Front End (MxFE®) for Broadband Applications
• Manufacturer: Analog Devices

Specifications of AD9878

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 29MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: QFP

REGISTER 0x00—INITIALIZATION
Bits 0 to 4: OSCIN Multiplier
This register field is used to program the on-chip clock
multiplier that generates the chip’s high frequency system clock,
f
by 16, program Register 0x00, Bits 4:0, to 0x10. The default
clock multiplier value, M, is 0x08. Valid entries range from 1 to
31. When M is set to 1, the PLL is disabled and internal clocks
are derived directly from OSCIN. The PLL requires 200 MCLK
cycles to regain frequency lock after a change in M. After the
recapture time of the PLL, the frequency of f
Bit 5: Reset
Writing 1 to this bit resets the registers to their default values
and restarts the chip. The reset bit always reads back 0. The bits
in Register 0x00 are not affected by this software reset. However,
a low level at the RESET pin forces all registers, including all
bits in Register 0x00, to their default states.
Bit 6: LSB First
Active high indicates SPI serial port access of instruction byte and
data registers is LSB first. Default low indicates MSB-first format.
Bit 7: SDIO Bidirectional
Active high configures the serial port as a 3-signal port with
the SDIO pin used as a bidirectional input/output pin. Default
low indicates that the serial port uses four signals with SDIO
configured as an input and SDO configured as an output.
REGISTER 0x01—CLOCK CONFIGURATION
Bits [5:0]: MCLK Divider
This register determines the output clock on the REFCLK pin.
At default 0 (R = 0), REFCLK provides a buffered version of the
OSCIN clock signal for other chips. The register can also be used
to divide the chip’s master clock f
between 2 and 63. The generated reference clock on REFCLK pin
can be used for external frequency controlled devices.
Bit 7: PLL Lock Detect
When this bit is set low, the REFCLK pin functions in its
default mode and provides an output clock with frequency
f
is configured to indicate whether the PLL is locked to f
this mode, the REFCLK pin should be low-pass filtered with an
RC filter of 1.0 kΩ and 0.1 µF. A low output on REFCLK indicates
that the PLL has achieved lock with f
REGISTER 0x02—POWER-DOWN
Unused sections of the chip can be powered down when the
corresponding bits are set high. This register has a default value
of 0x00, all sections active.
Bit 0: Power Down ADC12B Voltage Reference
Active high powers down the voltage reference circuit
for ADC12B.
SYSCLK
MCKL
/R, as described above. If this bit is set to 1, the REFCLK pin
. For example, to multiply the external crystal clock f
MCLK
by R, where R is an integer
OSCIN
.
SYSCLK
is stable.
OSCIN
OSCIN
. In
Rev. A | Page 15 of 36
Bit 1: Power Down ADC12A Voltage Reference
Active high powers down the voltage reference circuit for
the ADC12A.
Bit 2: Power Down ADC10
Active high powers down the 10-bit ADC.
Bit 3: Power Down ADC12B
Active high powers down the ADC12B.
Bit 4: Power Down ADC12A
Active high powers down the ADC12A.
Bit 5: Power Down Tx
Active high powers down the digital transmit section of the
chip, similar to the function of the PWRDN pin.
Bit 6: Power Down DAC Tx
Active high powers down the DAC.
Bit 7: Power Down PLL
Active high powers down the OSCIN multiplier.
REGISTER 0x03—FLAG CONTROL
Bit 0: Flag 0 Enable
When this bit is active high, the SIGDELT pin maintains a fixed
logic level determined directly by the MSB of the ∑-∆ control
word of Register 0x04.
Bit 1: Flag 1
The logic level of this bit is applied at the FLAG1 pin.
Bit 4: Flag 2
The logic level of this bit is applied at the FLAG2 pin.
Bit 5: Video Input into ADC12B
If the video input is enabled, setting this bit high sends the
signal applied to the VIDEO IN pin to the ADC12B. Otherwise,
the signal applied to the VIDEO IN pin is sent to the ADC12A.
REGISTER 0x04—∑-∆ CONTROL WORD
Bits [7:0]: ∑-∆ Control Word
The ∑-∆ control word is 8 bits wide and controls the duty cycle
of the digital output on the SIGDELT pin. Changes to the ∑-∆
control word take effect immediately for every register write.
∑-∆ output control words have a default value of 0. The control
words are in straight binary format, with 0x00 corresponding to
the bottom of scale or 0% duty cycle, and 0xFF corresponding
to the top of scale or near 100% duty cycle.
Bit 7: Flag 0 (∑-∆ Control Word MSB)
When the Flag 0 enable bit (Register 0x03, Bit 0) is set, the logic
level of this bit appears on the output of the SIGDELT pin.
AD9878