AD9878 Analog Devices, AD9878 Datasheet - Page 4

• Manufacturer Part Number: AD9878
• Description: Low Cost, 3.3 V, CMOS Mixed Signal Front End (MxFE®) for Broadband Applications
• Manufacturer: Analog Devices

Specifications of AD9878

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 29MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: QFP

AD9878
ELECTRICAL CHARACTERISTICS
V
R
Table 1.
PARAMETER
OSCIN and XTAL CHARACTERISTICS
Tx DAC CHARACTERISTICS
Tx MODULATOR CHARACTERISTICS
Tx GAIN CONTROL
10-BIT ADC CHARACTERISTICS
SET
AS
Frequency Range
Duty Cycle
Input Impedance
MCLK Cycle-to-Cycle Jitter (f
Maximum Sample Rate
Resolution
Full-Scale Output Current
Gain Error (Using Internal Reference)
Offset Error
Reference Voltage (REFIO Level)
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Output Capacitance
Phase Noise @ 1 kHz Offset, 42 MHz Carrier
Output Voltage Compliance Range
Wideband SFDR
Narrow-Band SFDR (±1 MHz Window)
I/Q Offset
Pass-Band Amplitude Ripple (f < f
Pass-Band Amplitude Ripple (f < f
Stop-Band Response (f > f
Gain Step Size
Gain Step Error
Settling Time, 1% (Full-Scale Step)
Resolution
Maximum Conversion Rate
Pipeline Delay
Analog Input
Dynamic Performance (A
= 3.3 V ± 5%, V
= 4.02 kΩ, maximum. Fine gain, 75 Ω DAC load.
5 MHz Analog Output, I
65 MHz Analog Output, I
5 MHz Analog Output, I
65 MHz Analog Output, I
Input Voltage Range
Differential Input Impedance
Full Power Bandwidth
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Reference Voltage Error, REFT10 to REFB10 (1.0 V)
DS
= 3.3 V ± 10%, f
IN
OUT
OUT
IQCLK
= −0.5 dBFS, f = 5 MHz)
OUT
OUT
MCLK
= 10 mA
= 10 mA
× 3/4)
= 10 mA
= 10 mA
derived from PLL)
IQCLK
IQCLK
OSCIN
/8)
/4)
= 27 MHz, f
SYSCLK
Temp
Full
25°C
25°C
25°C
Full
N/A
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
N/A
Full
N/A
Full
25°C
25°C
Full
Full
Full
Full
Full
Rev. A | Page 4 of 36
= 216 MHz, f
Test Level
II
II
III
III
II
N/A
II
I
I
I
III
III
III
III
II
II
II
II
II
II
II
II
II
III
III
III
N/A
II
N/A
II
III
III
II
II
II
II
I
MCLK
= 54 MHz (M = 8), ADC clock derived from OSCIN,
Min
3
35
232
4
−2.0
1.18
−0.5
62.4
50.3
71
61
50
29
57.6
9.3
65.7
Typ
50
100||3
6
12
10
−1
±1.0
1.23
±2.5
±8
5
−110
68
53.5
74
64
55
0.5
<0.05
1.8
10
4.5
2
4||2
90
59.7
9.6
−71.1
72.4
±4
Max
29
65
20
+2.0
1.28
+1.5
±0.1
±0.5
−63
−63.6
±100
MHz
%
MΩ||pF
ps rms
MHz
Bits
mA
% FS
V
LSB
LSB
pF
dBc/Hz
V
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
µs
Bits
MHz
ADC cycles
V
kΩ||pF
MHz
dB
Bits
dB
dB
mV
Unit
% FS
PPD