AD7866 Analog Devices, AD7866 Datasheet - Page 14

• Manufacturer Part Number: AD7866
• Description: Dual 1MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface
• Manufacturer: Analog Devices

Specifications of AD7866

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: SOP

AD7866
Digital Inputs
The digital inputs applied to the AD7866 are not limited by the
maximum ratings that limit the analog inputs. Instead, the digital
inputs applied can go to 7 V and are not restricted by the V
0.3 V limit as on the analog inputs. See maximum ratings.
Another advantage of SCLK, RANGE, REF SELECT, A0, and
CS not being restricted by the V
supply sequencing issues are avoided. If one of these digital inputs
is applied before V
would be on the analog inputs if a signal greater than 0.3 V were
applied prior to V
V
The AD7866 also has the V
voltage at which the serial interface operates. V
ADC to easily interface to both 3 V and 5 V processors. For
example, if the AD7866 was operated with a V
V
dynamic range with low voltage digital processors. For example,
the AD7866 could be used with the 2
V
REFERENCE CONFIGURATION OPTIONS
The AD7866 has various reference configuration options. The
REF SELECT pin allows the choice of using an internal 2.5 V
reference or applying an external reference, or even an individual
external reference for each on-chip ADC if desired. If the REF
SELECT pin is tied to AGND, then the on-chip 2.5 V reference
is used as the reference source for both ADC A and ADC B. In
addition, pins V
capacitors (100 nF, 470 nF, and 470 nF recommended,
respectively). If the REF SELECT pin is tied to a logic high, an
external reference can be supplied to the AD7866 through the
V
decoupling capacitors are required on D
However, if the V
is tied to a logic low, an individual external reference can be
applied to both ADC A and ADC B through pins D
D
For specified performance, the last configuration was used with
the same reference voltage applied to both D
The connections for the relevant reference pins are shown in the
typical connection diagrams. If the internal reference is being
used, the V
AGND very close to the V
in Figure 12.
DRIVE
DRIVE
DD
REF
CAP
of 5 V while still being able to interface to 3 V digital parts.
B, respectively. Table II summarizes these reference options.
pin to overdrive the on-chip reference, in which case
pin could be powered from a 3 V supply, allowing a large
REF
REF
pin should have a 100 nF capacitor connected to
Reference Option
Internal
Externally through V
Externally through
NOTES
1
2
Recommended value of decoupling capacitor = 100 nF.
Recommended value of decoupling capacitor = 470 nF.
REF
DD
D
, D
DD
CAP
.
CAP
pin is tied to AGND while REF SELECT
, there is no risk of latch-up, as there
A and/or D
A, and D
REF
DRIVE
pin. These connections are shown
DD
CAP
feature, which controls the
CAP
+ 0.3 V limit is that power
B must be tied to decoupling
REF
B
V
CAP
REF
A and D
REF SELECT
Low
High
Low
CAP
input range, with a
DD
DRIVE
A and D
of 5 V, the
Table II. Reference Selection
CAP
CAP
allows the
A and
B again.
CAP
DD
B.
+
V
Decoupling Capacitor
External Reference
AGND
–14–
REF
Figure 13 shows the connections required when an external
reference is applied to D
same reference voltage is applied at each pin; however, a different
voltage may be applied at each of these pins for each on-chip
ADC. An external reference applied at these pins may have a
range from 2 V to 3 V, but for specified performance it must be
within ± 1% of 2.5 V. Figure 14 shows the third option, which is
to overdrive the internal reference through the V
possible due to the series resistance from the V
internal reference. This external reference can have a range from
2 V to 3 V; but again, to get as close as possible to the specified
performance, a 2.5 V reference is desirable. D
decouple each on-chip reference buffer, as shown in Figure 15.
1
Figure 12. Relevant Connections when Using an
Internal Reference
Figure 13. Relevant Connections when Applying
an External Reference at D
Figure 14. Relevant Connections when Applying
an External Reference at V
V
470nF
470nF
V
REF
REF
D
Decoupling Capacitor
Decoupling Capacitor
External Reference A and/or
Reference B
470nF
470nF
100nF
CAP
CAP
A and D
A and D
D
D
V
CAP
CAP
REF
D
D
V
D
D
CAP
CAP
REF
V
CAP
CAP
REF
A
B
REF SELECT
A
B
A
B
AD7866
REF SELECT
AD7866
REF
CAP
CAP
CAP
AD7866
V
DRIVE
B
A and/or D
B. In this example, the
2
CAP
REF
REF
A and D
CAP
pin. This is
pin to the
B
REV. A
CAP
B