AD7866 Analog Devices, AD7866 Datasheet - Page 20

• Manufacturer Part Number: AD7866
• Description: Dual 1MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface
• Manufacturer: Analog Devices

Specifications of AD7866

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: SOP

AD7866
For example, if the ADSP-2189 had a 20 MHz crystal such that it
had a master clock frequency of 40 MHz, then the master cycle
time would be 25 ns. If the SCLKDIV register is loaded with the
value 3, an SCLK of 5 MHz is obtained and eight master clock
periods will elapse for every 1 SCLK period. Depending on the
throughput rate selected, if the timer register were loaded with the
value, 803, (803 + 1 = 804), for example, 100.5 SCLKs would
occur between interrupts and subsequently between transmit
instructions. This situation would result in nonequidistant
sampling as the transmit instruction is occurring on an SCLK
edge. If the number of SCLKs between interrupts were a whole
integer figure of N, equidistant sampling would be implemented
by the DSP.
AD7866 to TMS320C541
The serial interface on the TMS320C541 uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices like the AD7866. The
CS input allows easy interfacing between the TMS320C541 and
the AD7866 with no glue logic required. The serial ports of
the TMS320C541 are set up to operate in burst mode with internal
CLKX (Tx serial clock on serial port 0) and FSX0 (Tx frame sync
from serial port 0). The serial port control (SPC) registers must have
the following setup:
The format bit, FO, may be set to 1 to set the word length to
eight bits, in order to implement the power-down modes on the AD7866.
SPC0: FO = 0, FSM = 1, MCM = 1 and TxM = 1
SPC1: FO = 0, FSM = 1, MCM = 0 and TxM = 0
Figure 25. Interfacing the AD7866 to the TMS320C541
Figure 24. Interfacing the AD7866 to the ADSP-218x
*ADDITIONAL PINS OMITTED
*ADDITIONAL PINS OMITTED
FOR CLARITY
FOR CLARITY
AD7866*
AD7866*
D
D
D
V
D
V
SCLK
SCLK
OUT
DRIVE
OUT
DRIVE
OUT
OUT
CS
CS
A
A
B
B
TMS320C541*
TFS0
SCLK0
SCLK1
RFS0
RSF1
DR0
DR1
CLKX0
CLKR0
CLKX1
CLKR1
DR0
DR1
FSX0
FSR0
FSR1
ADSP-218x*
V
V
DD
DD
–20–
The connection diagram is shown in Figure 25. It should be noted
that for signal processing applications, it is imperative that the
frame synchronization signal from the TMS320C541 will provide
equidistant sampling. The V
same supply voltage as that of the TMS320C541. This allows the
ADC to operate at a higher voltage than the serial interface, i.e.,
TMS320C541, if necessary.
AD7866 to DSP-563xx
The connection diagram in Figure 26 shows how the AD7866
can be connected to the ESSI (synchronous serial interface) of
the DSP-563xx family of DSPs from Motorola. Each ESSI
(there are two on-board) is operated in synchronous mode
(bit SYN = 1 in CRB register) with internally generated word
length frame sync for both Tx and Rx (bits FSL1 = 0 and FSL0 = 0
in CRB). Normal operation of the ESSI is selected by making
MOD = 0 in the CRB. Set the word length to 16 by setting bits
WL1 = 1 and WL0 = 0 in CRA. To implement the power-down
modes on the AD7866, the word length can be changed to eight
bits by setting bits WL1 = 0 and WL0 = 0 in CRA. The FSP bit
in the CRB should be set to 1 to make the frame sync negative.
It should be noted that for signal processing applications, it is
imperative that the frame synchronization signal from the
DSP-563xx provide equidistant sampling.
In the example shown in Figure 26, the serial clock is taken from
the ESSI0, so the SCK0 pin must be set as an output, SCKD = 1,
while the SCK1 pin is set up as an input, SCKD = 0. The frame
sync signal is taken from SC02 on ESSI0, so SCD2 = 1, while
on ESSI1, SCD2 = 0, so SC12 is configured as an input. The
V
of the DSP-563xx. This allows the ADC to operate at a higher
voltage than the serial interface, i.e., DSP-563xx, if necessary.
APPLICATION HINTS
Grounding and Layout
The analog and digital supplies to the AD7866 are independent
and separately pinned out to minimize coupling between the analog
and digital sections of the device. The AD7866 has very good
immunity to noise on the power supplies as can be shown by the
PSRR vs. Supply Ripple Frequency plots, TPC 3a to TPC 4b.
However, care should be taken with regard to grounding and
layout.
The printed circuit board that houses the AD7866 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
DRIVE
pin of the AD7866 takes the same supply voltage as that
*ADDITIONAL PINS OMITTED
FOR CLARITY
Figure 26. Interfacing to the DSP-563xx
AD7866*
D
D
V
SCLK
OUT
OUT
DRIVE
CS
A
B
DRIVE
pin of the AD7866 takes the
SCK0
SCK1
SRD0
SRD1
SC02
SC12
DSP-563xx*
V
DD
REV. A