AD7866 Analog Devices, AD7866 Datasheet - Page 15

• Manufacturer Part Number: AD7866
• Description: Dual 1MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface
• Manufacturer: Analog Devices

Specifications of AD7866

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: SOP

If the on-chip 2.5 V reference is being used, and is to be applied
externally to the rest of the system, it may be taken from either
the V
from the V
elsewhere as it will not be capable of sourcing more than a few
microamps. If the reference voltage is taken from either the
D
pin is capable of sourcing current in the region of 100 µA; how-
ever, the larger the source current requirement, the greater the
voltage drop seen at the pin. The output impedance of each of
these pins is typically 50 Ω. In addition, this point represents
the actual voltage applied to the ADC internally so any voltage
drop due to the current load or disturbance due to a dynamic
load will directly affect the ADC conversion. For this reason, if a
large current source is necessary or a dynamic load is present, it
is recommended to use a buffer on the output to drive a device.
Examples of suitable external reference devices that may be ap-
plied at pins V
REF43, and AD1582.
MODES OF OPERATION
The mode of operation of the AD7866 is selected by controlling
the (logic) state of the CS signal during a conversion. There
are three possible modes of operation: normal mode, partial
power-down mode, and full power-down mode. The point at
which CS is pulled high after the conversion has been initiated
will determine which power-down mode, if any, the device will
enter. Similarly, if already in a power-down mode, CS can
control whether the device will return to normal operation or
remain in power-down. These modes of operation are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for differing application requirements.
REV. A
CAP
A pin or D
REF
pin or one of the D
REF
EXT REF
REF
pin, it must be buffered before being applied
CAP
Figure 15. Reference Circuit
100nF
, D
B pin, a buffer is not strictly necessary. Either
2.5V
REF
CAP
A, or D
D
D
V
SCLK
OUT
OUT
REF
CAP
CS
BUF A
BUF B
A
B
CAP
A or D
D
D
CAP
CAP
B are the AD780, REF192,
EXT REF
B
A
CAP
B pins. If it is taken
470nF
ADC A
ADC B
EXT REF
1
470nF
Figure 16. Normal Mode Operation
STATUS BITS AND CONVERSION RESULT
–15–
Normal Mode
This mode is intended for fastest throughput rate performance
since the user does not have to worry about any power-up times
with the AD7866 remaining fully powered all the time. Figure 16
shows the general diagram of the operation of the AD7866 in
this mode.
The conversion is initiated on the falling edge of CS, as described
in the Serial Interface section. To ensure that the part remains
fully powered up at all times, CS must remain low until at least
10 SCLK falling edges have elapsed after the falling edge of CS.
If CS is brought high any time after the 10th SCLK falling edge,
but before the 16th SCLK falling edge, the part will remain
powered up but the conversion will be terminated and D
and D
cycles are required to complete the conversion and access the
conversion result. The D
after 16 SCLK cycles have elapsed, but instead when CS is
brought high again. If CS is left low for another 16 SCLK cycles,
the result from the other ADC on board will also be accessed on
the same D
Interface section). The STATUS bits provided prior to each
conversion result will identify which ADC the following result
will be from. Once 32 SCLK cycles have elapsed, the D
will return to three-state on the 32nd SCLK falling edge. If CS is
brought high prior to this, the D
at that point. Thus, CS may idle low after 32 SCLK cycles, until
it is brought high again sometime prior to the next conversion
(effectively idling CS low), if so desired, since the bus will still
return to three-state upon completion of the dual result read.
Once a data transfer is complete and D
returned to three-state, another conversion can be initiated after
the quiet time, t
Partial Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then powered
down for a relatively long duration between these bursts of several
conversions. When the AD7866 is in partial power-down, all
analog circuitry is powered down except for the on-chip reference
and reference buffer.
To enter partial power-down, the conversion process must be
interrupted by bringing CS high anywhere after the second
falling edge of SCLK and before the tenth falling edge of SCLK
as shown in Figure 17. Once CS has been brought high in this
window of SCLKs, the part will enter partial power-down, the
conversion that was initiated by the falling edge of CS will be
10
OUT
B will go back into three-state. Sixteen serial clock
OUT
line, as shown in Figure 22 (see also the Serial
QUIET
, has elapsed by bringing CS low again.
OUT
16
line will not return to three-state
OUT
line will return to three-state
OUT
A and D
AD7866
OUT
B have
OUT
OUT
line
A