AD5669R Analog Devices, AD5669R Datasheet - Page 21

• Manufacturer Part Number: AD5669R
• Manufacturer: Analog Devices

Specifications of AD5669R

• Resolution (bits): 16bit
• Dac Update Rate: 166kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages
on its output, which gives an output range of 0 V to V
amplifier is capable of driving a load of 2 kΩ in parallel with
1000 pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figure 24 and Figure 25. The slew rate
is 1.5 V/μs with a ¼ to ¾ scale settling time of 10 μs.
SERIAL INTERFACE
The AD5629R/AD5669R have 2-wire I
interfaces (refer to The I
January 2000, available from Philips Semiconductor). The
AD5629R/AD5669R can be connected to an I
device under the control of a master device. See Figure 2 for a
timing diagram of a typical write sequence.
The AD5629R/AD5669R support standard (100 kHz) and fast
(400 kHz) modes. High speed operation is only available on
selected models. See the Ordering Guide for a full list of
models. Support is not provided for 10-bit addressing and
general call addressing.
The AD5629R/AD5669R each have a 7-bit slave address.
The parts have a slave address whose five MSBs are 10101,
and the two LSBs are set by the state of the A0 address pin,
which determines the state of the A0 and A1 address bits.
The facility to make hardwired changes to the A0 pin allows the
user to incorporate up to three of these devices on one bus, as
outlined in Table 7.
Table 7. ADDR Pin Settings
A0 Pin Connection
V
NC
GND
The 2-wire serial bus protocol operates as follows:
1.
DD
(CONTINUED)
(CONTINUED)
The master initiates data transfer by establishing a start
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address. The slave
SCL
SDA
START BY
MASTER
SDA
SCL
1
1
DB15 DB14 DB13 DB12
1
2
0
C-Bus Specification , Version 2.1,
1
SLAVE ADDRESS
FRAME 1
0
2
C-compatible serial
MOST SIGNIFICANT
1
DATA BYTE
FRAME 3
A1
0
1
1
DB11 DB10
A1
2
C bus as a slave
A0
DD
AD5629R/AD5669R
. The
A0
0
0
1
R/W
DB9
Figure 50. I
ACK. BY
Rev. A | Page 21 of 28
AD5629R/AD5669R
9
DB8
ACK. BY
2
C Write Operation
1
DB23
9
DB22 DB21 DB20 DB19 DB18 DB17
1
DB7
2.
3.
WRITE OPERATION
When writing to the AD5629R/AD5669R, the user must begin
with a start command followed by an address byte (R/ W = 0),
after which the DAC acknowledges that it is prepared to receive
data by pulling SDA low. The AD5629R/AD5669R require two
bytes of data for the DAC and a command byte that controls
various DAC functions. Three bytes of data must, therefore, be
written to the DAC, the command byte followed by the most
significant data byte and the least significant data byte, as shown in
Figure 50
AD5629R/AD5669R, a stop condition follows.
READ OPERATION
When reading data back from the AD5629R/AD5669R, the
user begins with a start command followed by an address byte
(R/ W = 1), after which the DAC acknowledges that it is prepared
to transmit data by pulling SDA low. Two bytes of data are then
read from the DAC, which are both acknowledged by the master as
shown in
DB6
address corresponding to the transmitted address responds
by pulling SDA low during the ninth clock pulse (this is
termed the acknowledge bit). At this stage, all other devices
on the bus remain idle while the selected device waits for
data to be written to or read from its shift register.
Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during
the low period of SCL and remain stable during the high
period of SCL.
When all data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10
a stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA
line remains high). The master brings the SDA line low
before the 10
clock pulse to establish a stop condition.
. After these data bytes are acknowledged by the
Figure 51
DB5
COMMAND BYTE
FRAME 2
LEAST SIGNIFICANT
DB4
th
DATA BYTE
FRAME 4
. A stop condition follows.
clock pulse and then high during the 10
DB3
DB2
AD5629R/AD5669R
DB16
DB1
AD5629R/AD5669R
AD5629R/AD5669R
ACK. BY
th
9
DB0
clock pulse to establish
ACK. BY
9
STOP BY
MASTER
th