AD5669R Analog Devices, AD5669R Datasheet - Page 7

• Manufacturer Part Number: AD5669R
• Manufacturer: Analog Devices

Specifications of AD5669R

• Resolution (bits): 16bit
• Dac Update Rate: 166kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

I
V
Table 4.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
SCL
2
1
2
3
4
5
6
7
8
9
10
11
11A
12
13
14
15
SP
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC
behavior of the part.
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.
C TIMING CHARACTERISTICS
DD
2
1
= 2.7 V to 5.5 V; all specifications T
Conditions
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Fast mode
Min
4
0.6
4.7
1.3
250
100
0
0
4.7
0.6
4
0.6
4.7
1.3
4
0.6
10
10
300
300
20
20
0
MIN
to T
Max
100
400
3.45
0.9
1000
300
300
300
1000
300
1000
300
300
300
50
MAX
, f
SCL
= 400 kHz, unless otherwise noted.
Unit
kHz
kHz
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. A | Page 7 of 28
Description
Serial clock frequency
t
t
t
t
t
t
t
t
t
t
t
t
after an acknowledge bit
t
LDAC pulse width low
Falling edge of ninth SCL clock pulse of last byte of a valid write to
the LDAC falling edge
CLR pulse width low
Pulse width of spike suppressed
HIGH
LOW
SU;DAT
HD;DAT
SU;STA
HD;STA
BUF
SU;STO
RDA
FDA
RCL
RCL1
FCL
, fall time of SCL signal
, rise time of SCL signal
, bus-free time between a stop and a start condition
, fall time of SDA signal
, rise time of SDA signal
, SCL low time
, rise time of SCL signal after a repeated start condition and
, SCL high time
, setup time for a repeated start condition
, setup time for a stop condition
, data setup time
, hold time (repeated) start condition
, data hold time
AD5629R/AD5669R