AD5663R Analog Devices, AD5663R Datasheet - Page 23

• Manufacturer Part Number: AD5663R
• Manufacturer: Analog Devices

Specifications of AD5663R

• Resolution (bits): 16bit
• Dac Update Rate: 220kSPS
• Dac Settling Time: 4µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

Table 13. 24-Bit Input Shift Register Contents of Power Up/Down Function
MSB
DB23 to
DB22
x
Don’t
care
Table 14. 24-Bit Input Shift Register Contents for LDAC Setup Command
MSB
DB23 to
DB22
x
Don’t care
LDAC FUNCTION
The AD5623R/AD5643R/AD5663R DACs have double-
buffered interfaces consisting of two banks of registers: input
registers and DAC registers. The input registers are connected
directly to the input shift register, and the digital code is
transferred to the relevant input register on completion of a
valid write sequence. The DAC registers contain the digital code
used by the resistor strings.
Access to the DAC registers is controlled by the LDAC pin.
When the LDAC pin is high, the DAC registers are latched and
the input registers can change state without affecting the
contents of the DAC registers. When LDAC is brought low,
however, the DAC registers become transparent and the
contents of the input registers are transferred to them. The
double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to one of the input registers individually and then, by bringing
LDAC low when writing to the other DAC input register, all
outputs will update simultaneously.
These parts each contain an extra feature whereby a DAC
register is not updated unless its input register has been updated
since the last time LDAC was brought low. Normally, when LDAC
is brought low, the DAC registers are filled with the contents of
the input registers. In the case of the AD5623R/AD5643R/
AD5663R, the DAC register updates only if the input register
has changed since the last time the DAC register was updated,
thereby removing unnecessary digital crosstalk.
The outputs of all DACs can be simultaneously updated, using
the hardware LDAC pin.
Synchronous LDAC
The DAC registers are updated after new data is read in on the
falling edge of the 24th SCLK pulse. LDAC can be permanently
low or pulsed as shown in
DB21
1
Command bits (C2 to C0)
DB21
1
Command bits (C2 to C0)
DB20
0
Figure 2
DB20
1
DB19
0
.
DB18
x
Address bits (A2 to A0)
Don’t care
DB19
0
DB17
x
x
DB110
Address bits (A3 to A0)
Don’t care
DB16
x
Rev. D | Page 23 of 32
DB17
x
DB15 to
DB6
x
Don’t
care
Asynchronous LDAC
The outputs are not updated at the same time that the input
registers are written to. When LDAC goes low, the DAC
registers are updated with the contents of the input register.
The LDAC register gives the user full flexibility and control over
the hardware LDAC pin. This register allows the user to select
which combination of channels to simultaneously update when
the hardware LDAC pin is executed. Setting the LDAC bit
register to 0 for a DAC channel means that the update of this
channel is controlled by the LDAC pin. If this bit is set to 1, this
channel synchronously updates; that is, the DAC register is
updated after new data is read in, regardless of the state of the
LDAC pin. It effectively sees the LDAC pin as being pulled low.
See
flexibility is useful in applications where the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating.
Writing to the DAC using Command 110 loads the 2-bit LDAC
register [DB1:DB0]. The default for each channel is 0; that is,
the LDAC pin works normally. Setting the bits to 1 means the
DAC register is updated, regardless of the state of the LDAC
pin. See
the
Table 15. LDAC Register Mode of Operation
LDAC Bits
(DB1 to DB0)
0
1
DB16
x
LDAC register setup command.
Table 15
DB5
Power-down
mode
PD1
Table 14
for the
DB15 to DB2
x
Don’t care
DB4
PD0
LDAC Pin
1/0
x = don’t care
for contents of the input shift register during
AD5623R/AD5643R/AD5663R
LDAC register mode of operation. This
DB3
x
Don’t care
DB1
DAC B
Set DAC to 0 or 1 for required
mode of operation
DB2
x
LDAC Operation
Determined by LDAC pin
The DAC registers are updated
after new data is read in on the
falling edge of the 24th SCLK
pulse.
DB1
DAC B
Power down/Power up
channel selection;
set bit to 1 to select
channel
DB0
DAC A
DB0
DAC A
LSB
LSB