CS8420-CSZ Cirrus Logic Inc, CS8420-CSZ Datasheet - Page 47

• Manufacturer Part Number: CS8420-CSZ
• Description: IC SAMPLE RATE CONVERTER 28SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-CSZ

• Package / Case: 28-SOIC
• Applications: CD-R, DAT, DVD, MD, VTR
• Mounting Type: Surface Mount
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Resolution: 17 bit to 24 bit
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Bandwidth: 20kHz
• Rohs Compliant: Yes
• Audio Control Type: Volume
• Dc: 0841
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1782 - EVALUATION BOARD FOR CS8420
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1125-5

Overall Device Control:
H/S - Hardware or Software Control Mode Select *
RST - Reset Input *
INT - Interrupt Output
Audio Input Interface:
SDIN - Serial Audio Input Port Data Input
ISCLK - Serial Audio Input Port Bit Clock input or output
ILRCK - Serial Audio Input Port Left/Right Clock input or output
AES3/SPDIF Receiver Interface:
RXP, RXN - Differential Line Receiver Inputs
RERR - Receiver Error Indicator
EMPH - Pre-emphasis Indicator Output
Audio Output Interface:
SDOUT - Serial Audio Output Port Data Output
DS245PP2
The H/S pin determines the method of controlling the operation of the CS8420, and the method of
accessing CS and U data. In software mode, device control and CS and U data access is primarily via
the control port, using a microcontroller. In hardware mode, alternate modes and access to CS and U
data is provided by pins. This pin should be permanently tied to VD+ or DGND.
When RST is low, the CS8420 enters a low power mode and all internal states are reset. On initial
power up, RST must be held low until the power supply is stable, and all input clocks are stable in
frequency and phase. This is particularly true in hardware mode with multiple CS8420 devices, where
synchronization between devices is important.
The INT output pin indicates errors and key events during the operation of the CS8420. All bits affecting
INT are maskable via control registers. The condition(s) that initiated interrupt are readable via a control
register. The polarity of the INT output, as well as selection of a standard or open drain output, is set via
a control register. Once set true, the INT pin goes false only after the interrupt status registers have
been read, and the interrupt status bits have returned to zero.
Audio data serial input pin.
Serial bit clock for audio data on the SDIN pin.
Word rate clock for the audio data on the SDIN pin. The frequency will be at the input sample rate (Fsi)
Differential line receiver inputs, carrying AES3 type data.
When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is
updated once per sub-frame of incoming AES3 data. Conditions that can cause RERR to go high are:
validity, parity error, bi-phase coding error, confidence, QCRC and CCRC errors, as well as loss of lock
in the PLL. Each condition may be optionally masked from affecting the RERR pin using the Receiver
Error Mask Register. The RERR pin tracks the status of the unmasked errors: the pin goes high as soon
as an unmasked error occurs and goes low immediately when all unmasked errors go away.
EMPH is low when the incoming AES3 data indicates the presence of 50/15 s pre-emphasis. When
the AES3 data indicates the absence of pre-emphasis or the presence of other than 50/15
emphasis EMPH is high. This is also a start-up option pin, and requires a 47 k
or DGND, which determines the AD2 address bit for the control port in I
Audio data serial output pin.
2
C mode.
resistor to either VD+
CS8420
s pre-
47