CS8420-CSZ Cirrus Logic Inc, CS8420-CSZ Datasheet - Page 48

• Manufacturer Part Number: CS8420-CSZ
• Description: IC SAMPLE RATE CONVERTER 28SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-CSZ

• Package / Case: 28-SOIC
• Applications: CD-R, DAT, DVD, MD, VTR
• Mounting Type: Surface Mount
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Resolution: 17 bit to 24 bit
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Bandwidth: 20kHz
• Rohs Compliant: Yes
• Audio Control Type: Volume
• Dc: 0841
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1782 - EVALUATION BOARD FOR CS8420
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1125-5

OSCLK - Serial Audio Output Port Bit Clock input or output
OLRCK - Serial Audio Output Port Left/Right Clock input or output
AES3/SPDIF Transmitter Interface:
TCBL - Transmit Channel Status Block Start
TXN, TXP - Differential Line driver outputs
Control Port Signals:
SCL/CCLK - Control Port clock
AD0/CS - Address Bit 0 (I
AD1/CDIN - Address Bit 1 (I
SDA/CDOUT - Serial Control Data I/O (I
Miscellaneous pins:
U - User Data
48
Serial bit clock for audio data on the SDOUT pin.
Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate
(Fso)
This pin can be configured as an input or output. When operated as output, TCBL is high during the first
sub-frame of a transmitted channel status block, and low at all other times. When operated as input,
driving TCBL high for at least three OMCK (or RMCK, depending on which clock is operating the AES3
encoder block) clocks will cause the next transmitted sub-frame to be the start of a channel status
block.
Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420
is in the reset state.
SCL/CCLK is the serial control interface clock, and is used to clock control data bits into and out of the
CS8420.
A falling edge on this pin puts the CS8420 into SPI control port mode. With no falling edge, the CS8420
defaults to I
control port interface on the CS8420.
In I
interface
In I
resistor to VD+. In SPI mode, CDOUT is the output data from the control port interface on the CS8420.
The U pin may optionally be used to input User data for transmission by the AES3 transmitter, see
Figure 22 for timing information. Alternatively, the U pin may be set to output User data from the AES3
receiver, see Figure 21 for timing information. If not driven, a 47k
for the U pin, since the default state of the UD direction bit sets the U pin as an input. The pull-down
resistor ensures that the transmitted user data will be zero. If the U pin is always set to be an output,
thereby causing the U bit manager to be the source of the U data, then the resistor is not necessary.
The U pin should not be tied directly to ground, in case it is programmed to be an output, and
subsequently tries to output a logic high. This situation may affect the long term reliability of the device.
If the U pin is driven by a logic level output, then a 100
2
2
C mode, AD1 is a chip address pin. In SPI mode, CDIN is the input data line for the control port
C mode, SDA is the control I/O data line. SDA is open drain, and requires an external pull-up
2
C mode. In I
2
C) / Control Port Chip Select (SPI)
2
2
C) / Serial Control data in (SPI)
C mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the
2
C) / data out (SPI)
series resistor is recommended.
pull-down resistor is recommended
CS8420
DS245PP2