AD5445 Analog Devices, AD5445 Datasheet - Page 19

• Manufacturer Part Number: AD5445
• Description: High Bandwidth CMOS 12-Bit Parallel Interface Multiplying D/A Converter
• Manufacturer: Analog Devices

Specifications of AD5445

• Resolution (bits): 12bit
• Dac Update Rate: 20.4MSPS
• Dac Settling Time: 80ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

Data Sheet
BIPOLAR OPERATION
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and some external resistors, as shown in Figure 50.
In this circuit, the second amplifier, A2, provides a gain of 2.
Biasing the external amplifier with an offset from the reference
voltage, results in full 4-quadrant multiplying operation. The
transfer function of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from code zero (V
(V
where D is the fractional representation of the digital word
loaded to the DAC and n is the resolution of the DAC.
When V
multiplication.
Table 8 shows the relationship between digital code and the
expected output voltage for bipolar operation (AD5424,
8-bit device).
Table 8. Bipolar Code Table
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
OUT
D = 0 to 255 (8-bit AD5424)
V
= 0 V) to full scale (V
OUT
= 0 to 1023 (10-bit AD5433)
= 0 to 4095 (12-bit AD5445)
IN
is an ac signal, the circuit performs 4-quadrant
=
(
V
REF
×
D
2 /
V
±10V
REF
n
−1
OUT
)
Analog Output (V)
+V
0
–V
–V
−
= +V
V
OUT
R1
REF
REF
REF
NOTES:
1.
2.
3.
REF
R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR V
MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.
C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS
A HIGH SPEED AMPLIFIER.
(127/128)
(128/128)
(127/128)
= –V
INPUTS
V
REF
DATA
REF
).
REF
V
DD
AD5424/
AD5433/
) to midscale
AD5445
R/W
V
DD
Figure 50. Bipolar Operation (4-Quadrant Multiplication)
CS
OUT
= 0V WITH CODE 10000000 LOADED TO DAC.
GND
R
FB
20kΩ
I
I
R3
OUT
OUT
1
2
R2
Rev. C | Page 19 of 28
C1
AGND
A1
Stability
In the I-to-V configuration, the I
node of the op amp must be connected as closely as possible and
proper PCB layout techniques must be employed. Since every code
change corresponds to a step function, gain peaking may occur
if the op amp has limited GBP and there is excessive parasitic
capacitance at the inverting node. This parasitic capacitance
introduces a pole into the open-loop response, which can cause
ringing or instability in closed-loop applications.
An optional compensation capacitor, C1, can be added in parallel
with R
small a value of C1 can produce ringing at the output, while too
large a value can adversely affect the settling time. C1 should be
found empirically, but 1 pF to 2 pF is generally adequate for
compensation.
10kΩ
R4
FB
for stability, as shown in Figure 49 and Figure 50. Too
A2
20kΩ
R5
V
OUT
AD5424/AD5433/AD5445
= –V
REF
OUT
TO +V
of the DAC and the inverting
REF