AD9751 Analog Devices, AD9751 Datasheet

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... CMOS process. It operates from a single supply of 3 3.6 V and consumes 155 mW of power. PRODUCT HIGHLIGHTS 1. The AD9751 is a member of a pin compatible family of high speed TxDAC+s, providing 10-, 12-, and 14-bit resolution. 2. Ultrahigh Speed 300 MSPS Conversion Rate. 3. Dual 10-Bit Latched, Multiplexed Input Ports. The AD9751 features a flexible digital interface allowing high speed data conversion through either a single or dual port input ...

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... AD9751–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) 2 Full-Scale Output Current Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT ...

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... Specifications subject to change without notice. REV AVDD = DVDD = CLKVDD = 3.3 V, PLLVDD = MIN MAX Transformer-Coupled Output, 50 Doubly Terminated, unless otherwise noted.) Min ) 300 –3– AD9751 = 20 mA, Differential OUTFS Typ Max Unit MSPS pV-s 2 pA/√Hz 30 pA/√Hz ...

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... AD9751 DIGITAL SPECIFICATIONS Parameter DIGITAL INPUTS Logic 1 Logic 0 Logic 1 Current Logic 0 Current Input Capacitance Input Setup Time ( 25° Input Hold Time ( 25° Latch Pulsewidth ( 25°C LPW A Input Setup Time (t PLLVDD = 0 V Input Hold Time (t PLLVDD = 0 V), T ...

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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9751 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

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... PLLVDD 48 CLKVDD PIN CONFIGURATION RESET 1 PIN 1 CLK+ 2 IDENTIFIER CLK– 3 DCOM 4 DVDD 5 AD9751 PLLLOCK 6 TOP VIEW 7 (Not to Scale) P1B8 8 P1B7 9 P1B6 10 P1B5 11 P1B4 PIN FUNCTION DESCRIPTIONS Description Internal Clock Divider Reset ...

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... CLK– DIGITAL DATA INPUTS MINI TEKTRONIX DG2020 CIRCUITS OR T1-1T AWG2021 w/OPTION 4 PLL ENABLED LECROY 9210 PULSE GENERATOR PLL DISABLED (FOR DATA RETIMING) Figure 2. Basic AC Characterization Test Setup –7– AD9751 MINI TO ROHDE & CIRCUITS SCHWARZ I T1-1T OUTA FSEA30 SPECTRUM I OUTB 50 ANALYZER PLLVDD ...

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... AD9751–Typical Performance Characteristics 90 0dBFS 80 70 –6dBFS –12dBFS (MHz) OUT TPC 1. Single-Tone SFDR vs OUT MSPS; Single Port Mode DAC 90 80 200MSPS 70 60 65MSPS 50 300MSPS 100 120 140 f (MHz) OUT TPC 4. SFDR vs. f ...

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... OUT TPC 14. SFDR vs OUTFS DAC 300 MSPS @ 0 dBFS 0.18 0.14 0.10 0.06 0.02 –0.02 0 127 255 383 511 639 767 CODE TPC 17. Typical DNL –9– AD9751 90 80 26MHz/27MHz 40MHz/41MHz @ 130MSPS @ 200MSPS 60MHz/61MHz @ 300MSPS 40 0 –20 –18 –16 –14 –12 –10 –8 A (dBm) OUT TPC 12 ...

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... AD9751 FUNCTIONAL DESCRIPTION Figure 3 shows a simplified block diagram of the AD9751. The AD9751 consists of a PMOS current source array capable of providing full-scale current, I divided into 31 equal sources that make up the five most signifi- cant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an MSB cur- rent source ...

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... PLL to generate the 2× clock needed for the DAC output latch. Figure 7 defines the input and output timing for the AD9751 with the PLL active. CLK in Figure 7 represents the clock that is generated external to the AD9751. The input data at both Ports 1 and 2 is latched on the same CLK rising edge. CLK may be applied as a single-ended signal by tying CLK– ...

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... CLK inputs at the desired DAC output update rate. The speed and timing of the data present at input Ports 1 and 2 is now dependent on whether or not the AD9751 is interleaving the digital input data or only responding to data on a single port. Figure functional block diagram of the AD9751 clock control circuitry with the PLL disabled ...

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... PLLLOCK. REV. C NONINTERLEAVED MODE WITH PLL DISABLED If the data at only one port is required, the AD9751 interface can operate as a simple double-buffered latch with no interleaving. On the rising edge of the 1× clock, input latch updated with the present input data (depending on the state of DIV0/ DIV1) ...

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... The negative output compliance range of –1 set by the breakdown limits of the CMOS process. and Operation beyond this maximum limit may result in a break- OUTA down of the output stage and affect the reliability of the AD9751. , DIFF The positive output compliance range is slightly dependent on OUTA the full-scale output current, I nominal 1 ...

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... CLK+ and CLK– should be biased to CLKVDD/2 via a resistor divider network, as shown in Figure 15b. Because the output of the AD9751 can be updated 300 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. The driv- ...

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... DAC Figure 19. PLLVDD vs. f APPLYING THE AD9751 OUTPUT CONFIGURATIONS The following sections illustrate some typical output configura- tions for the AD9751. Unless otherwise noted assumed that I OUTFS ing the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration ...

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... The differential circuit shown in Figure 22 provides the nec- essary level-shifting required in a single-supply system. In this case, AVDD, which is the positive analog supply for both the AD9751 and the op amp, is also used to level-shift the differ- ential output of the AD9751 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. ...

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... PSRR of the DAC at 250 kHz, which Figure 25, becomes Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9751 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a sys- tem ...

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... In Figure 29, the adjacent channel power ratio (ACPR) at the output of the AD9751 is measured dB. The limita- tion on making a measurement of this type is often not the DAC but the noise inherent in creating the digital data record using computer tools ...

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... QAM with the BER of 1e-6, if the E/N ratio is much greater than the worst-case SFDR, the noise will dominate the BER calculation. The AD9751 has a worst-case in-band SFDR the upper end of its frequency spectrum (see TPCs 2 and 3). When Cu1 ...

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... Port 1 (P1), Pin 33. By inserting the EDGE jumper (JP1), this clock will be applied to the CLK+ input of the AD9751. JP3 should be set in its SE position in this application to bias CLK– to half the supply voltage. The AD9751’s PLL clock multiplier can be enabled by inserting JP7 in the IN position ...

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... P1B07 1B05 13 P1B06 3 14 1B04 P1B05 15 4 1B03 P1B04 16 5 P1B03 1B02 17 P1B02 6 18 1B01 P1B01 AD9751/AD9753/AD9755 19 7 P1B00 LSB 1B00 20 8 DVDD PLANE 21 1O16 MSB 10 P2B13 24 1O17 P2B12 P2B11 RN9 P2B10 VALUE ...

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... DVDD PLANE TP15 RED AVDD PLANE TP16 BLK TP17 RED CLKVDD JP7 TP11 PLLVDD PLANE B BLK 3 Figure 35. Evaluation Board Clock Circuitry –23– AD9751 CLK JP4 PGND BYPASS CAPS PINS 5, 6 PINS 21 ...

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... AD9751 Figure 36. Evaluation Board, Assembly—Top Figure 37. Evaluation Board, Assembly—Bottom –24– REV. C ...

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... Figure 39. Evaluation Board, Layer 2, Ground Plane REV. C Figure 38. Evaluation Board, Top Layer –25– AD9751 ...

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... AD9751 Figure 40. Evaluation Board, Layer 3, Power Plane Figure 41. Evaluation Board, Bottom Layer –26– REV. C ...

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... REV. C OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.75 1.60 0.60 MAX 0.45 1 SEATING PLANE 10 6 0.20 2 0.09 VIEW 0.08 MAX 0.50 COPLANARITY BSC VIEW A COMPLIANT TO JEDEC STANDARDS MS-026BBC –27– AD9751 9.00 BSC PIN 1 TOP VIEW 7.00 BSC SQ (PINS DOWN 0.27 0.22 0.17 ...

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... AD9751 Revision History Location 9/03—Data Sheet changed from REV REV. C. Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to Figure Changes to Figure 1/03—Data Sheet changed from REV REV. B. Changes to Figure Changes to Figure Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3/02—Data Sheet changed from REV REV. A. ...