AD9751 Analog Devices, AD9751 Datasheet - Page 22

• Manufacturer Part Number: AD9751
• Manufacturer: Analog Devices

Specifications of AD9751

• Resolution (bits): 10bit
• Dac Update Rate: 300MSPS
• Dac Settling Time: 11ns
• Max Pos Supply (v): +3.6V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

AD9751
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
2
4
6
8
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
11
13
15
17
19
23
25
27
29
33
35
37
39
21
31
11
13
15
17
19
21
23
25
27
29
33
35
37
39
31
1
3
5
7
9
1
3
5
7
9
1O15
1O16
1O17
2B13
2B12
2B11
2B10
2B09
2B08
2B07
2B06
2B05
2B04
2B03
2B02
2B01
2B00
1B13
1B12
1B11
1B10
1B09
1B08
1B07
1B06
1B05
1B04
1B03
1B02
1B01
1B00
VALUE
VALUE
VALUE
VALUE
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
RN10
RN7
RN1
RN4
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
9
9
9
9
P2OUT15
P2OUT16
P1B05
P1B04
P1B03
P1B02
P1B01
P1B00
OUT15
OUT16
P2B04
P2B03
P2B02
P2B01
P2B00
P1B13
P1B12
P1B11
P1B10
P1B09
P1B08
P1B07
P1B06
P2B13
P2B12
P2B11
P2B10
P2B09
P2B08
P2B07
P2B06
P2B05
10
10
10
10
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
VALUE
VALUE
1
2
3
4
5
6
7
8
9
VALUE
VALUE
RN11
RN5
RN2
RN8
1O15
JP10
2OUT15
2OUT16
2B05
2B04
2B03
2B02
2B01
2B00
2B09
2B08
2B07
2B06
1B13
1B12
1B11
1B10
1B09
1B08
1B07
1B06
1B05
1B04
1B03
1B02
1B01
1B00
2B13
2B12
2B11
2B10
1O17
1O16
Figure 34. Evaluation Board Circuitry
10
10
10
10
VALUE
1
2
3
4
5
6
7
8
9
VALUE
1
2
3
4
5
6
7
8
9
VALUE
1
2
3
4
5
6
7
8
9
VALUE
1
2
3
4
5
6
7
8
9
RN12
RN3
RN6
RN9
DVDD PLANE
P1B13 MSB
P2B13
P2B12
P2B11
P2B10
P2B09
P2B08
P2B07
P2B06
P2B05
P2B04
P2B03
P2B02
P2B01
P2B00 LSB
P1B12
P1B11
P1B10
P1B09
P1B08
P1B07
P1B06
P1B05
P1B04
P1B03
P1B02
P1B01
P1B00 LSB
MSB
NOTES
1. ALL DIGITAL INPUTS FROM RN1–RN12
2. ALL DECOUPLING CAPS TO BE LOCATED
3. CONNECT GNDS UNDER DUT USING
4. CREATE PLANE CAPACITOR WITH 0.007"
MUST BE OF EQUAL LENGTH.
AS CLOSE AS POSSIBLE TO DUT,
PREFERABLY UNDER DUT ON BOTTOM
SIGNAL LAYER.
BOTTOM SIGNAL LAYER.
DIELECTRIC BETWEEN LAYERS 2 AND 3.
–22–
DGND: 3,4,5
13
14
15
16
17
18
19
20
21
22
23
24
TP4
12 11 10 9 8
AD9751/AD9753/AD9755
25 26 27 28 29 30 31 32 33 34 35 36
BLK
TP5
J1
BLK
2
1
TP6
DVDD PLANE
7 6 5 4
U1
BLK
TP7
CLK–
BLK
3 2 1
CLK+
TP8
RESET
BLK
48
47
46
45
44
43
42
41
40
39
38
37
TP9
LPF
IA
IB
BLK
AVDD PLANE
CLKVDD
DIV1
DIV0
1
1
PLLVDD PLANE
FSADJ
REFIO
TP10
A B
A B
EDGE
JP8
JP9
EXT
2
2
10pF
BLK
50
C10
P
R3
3
3
TP1
TP2
2
OUT16
TP12
A
B
WHT
WHT
R5
392
C11
1.0 F
BLK
1
3
R4
50
P
JP5
OPT
R10
1.91k
AVDD_PLANE
0.1 F
C12
R1
WHT
NOTE:
SHIELD AROUND
R5 AND C11 ARE
CONNECTED TO
PLLVDD PLANE
RESET
50
10pF
R2
C9
3
2
1
TP3
BL1
BL2
S
T1
P
4
6
REV. C
1
I
2
OUT
J5