AD5336

Manufacturer Part NumberAD5336
Description
ManufacturerAnalog Devices
AD5336 datasheet
 


Specifications of AD5336

Resolution (bits)10bitDac Update Rate143kSPS
Dac Settling Time7µsMax Pos Supply (v)+5.5V
Single-supplyYesDac TypeVoltage Out
Dac Input FormatPar  
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FEATURES
AD5334: Quad 8-Bit DAC in 24-Lead TSSOP
AD5335: Quad 10-Bit DAC in 24-Lead TSSOP
AD5336: Quad 10-Bit DAC in 28-Lead TSSOP
AD5344: Quad 12-Bit DAC in 28-Lead TSSOP
Low Power Operation: 500 A @ 3 V, 600 A @ 5 V
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
or 0–2 V
Output Range: 0–V
REF
REF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: –40 C to +105 C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GAIN
DB
7
.
. .
DB
0
CS
WR
INTER-
FACE
A0
LOGIC
A1
CLR
LDAC
.
*Protected by U.S. Patent Number 5,969,657
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
2.5 V to 5.5 V, 500 A, Parallel Interface
Quad Voltage-Output 8-/10-/12-Bit DACs
AD5334/AD5335/AD5336/AD5344*
GENERAL DESCRIPTION
The AD5334/AD5335/AD5336/AD5344 are quad 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply con-
suming just 500 µA at 3 V, and feature a power-down mode that
further reduces the current to 80 nA. These devices incorporate
an on-chip output buffer that can drive the output to both sup-
ply rails.
The AD5334/AD5335/AD5336/AD5344 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of WR.
The GAIN pin on the AD5334 and AD5336 allows the output
range to be set at 0 V to V
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.
On the AD5334, AD5335 and AD5336 an asynchronous CLR
input is also provided. This resets the contents of the Input
Register and the DAC Register to all zeros. These devices also
incorporate a power-on-reset circuit that ensures that the DAC
output powers on to 0 V and remains there until valid data is
written to the device.
The AD5334/AD5335/AD5336/AD5344 are available in Thin
Shrink Small Outline Packages (TSSOP).
AD5334 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
V
A/B
REF
POWER-ON
RESET
DAC
INPUT
8-BIT
BUFFER
REGISTER
REGISTER
DAC
INPUT
DAC
8-BIT
BUFFER
REGISTER
REGISTER
DAC
DAC
INPUT
8-BIT
8-BIT
BUFFER
REGISTER
REGISTER
DAC
DAC
INPUT
DAC
8-BIT
BUFFER
REGISTER
REGISTER
DAC
V
C/D
REF
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
or 0 V to 2 × V
.
REF
REF
V
DD
AD5334
V
A
OUT
V
B
OUT
V
C
OUT
V
D
OUT
TO ALL DACS
AND BUFFERS
POWER-DOWN
LOGIC
PD
GND
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000

AD5336 Summary of contents

  • Page 1

    ... The AD5334/AD5335/AD5336/AD5344 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR. The GAIN pin on the AD5334 and AD5336 allows the output range to be set Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin ...

  • Page 2

    ... See Terminology section. 2 Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C. 3 Linearity is tested using a reduced code range: AD5334 (Code 8 to 255); AD5335/AD5336 (Code 28 to 1023); AD5344 (Code 115 to 4095 specifications tested with outputs unloaded. 5 This corresponds to x codes ...

  • Page 3

    ... LDAC 2 LDAC CLR A0, A1 NOTES Figure 1. Parallel Interface Timing Diagram –3– AD5334/AD5335/AD5336/AD5344 to T MIN MAX Conditions/Comments See Figure 20 REF 1/4 Scale to 3/4 Scale Change ( 1/4 Scale to 3/4 Scale Change (100 H to 300 H) 1/4 Scale to 3/4 Scale Change (100 H to 300 H) 1/4 Scale to 3/4 Scale Change (400 H to C00 H) 1 LSB Change Around Major Carry = 2 V ± ...

  • Page 4

    ... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5334/AD5335/AD5336/AD5344 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

  • Page 5

    ... Eight Parallel Data Inputs GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V CLR 24 Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros. REV. 0 AD5334/AD5335/AD5336/AD5344 V A/B V REF DD AD5334 8-BIT BUFFER V ...

  • Page 6

    ... AD5334/AD5335/AD5336/AD5344 AD5335 FUNCTIONAL BLOCK DIAGRAM POWER-ON RESET HIGH BYTE REGISTER LOW BYTE DAC . . REGISTER REGISTER HIGH BYTE REGISTER WR A0 LOW BYTE DAC REGISTER REGISTER INTER- A1 FACE LOGIC HIGH BYTE HBEN REGISTER LOW BYTE DAC REGISTER REGISTER HIGH BYTE REGISTER ...

  • Page 7

    ... BUFFER V OUT DAC 10-BIT BUFFER V DAC OUT TO ALL DACS AND BUFFERS POWER-DOWN LOGIC GND REF REF AD5336 PIN FUNCTION DESCRIPTIONS is the MSB of these 10 bits. 9 –7– AD5336 PIN CONFIGURATION V D CLR 1 28 REF GAIN REF ...

  • Page 8

    ... AD5334/AD5335/AD5336/AD5344 AD5344 FUNCTIONAL BLOCK DIAGRAM POWER-ON RESET INPUT DAC . . REGISTER . REGISTER . INPUT DAC REGISTER REGISTER WR INTER- FACE A0 LOGIC INPUT DAC A1 REGISTER REGISTER INPUT DAC REGISTER REGISTER LDAC Pin No. Mnemonic Function Unbuffered Reference Input for DAC D. REF Unbuffered Reference Input for DAC C. ...

  • Page 9

    ... DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. This is illus- trated in Figure 2. ACTUAL OUTPUT VOLTAGE IDEAL DAC CODE Figure 2. Gain Error REV. 0 AD5334/AD5335/AD5336/AD5344 OUTPUT VOLTAGE POSITIVE OFFSET Figure 3. Positive Offset Error and Gain Error OUTPUT VOLTAGE NEGATIVE OFFSET ...

  • Page 10

    ... AD5334/AD5335/AD5336/AD5344 OFFSET ERROR DRIFT This is a measure of the change in Offset Error with changes in temperature expressed in (ppm of full-scale range)/°C. GAIN ERROR DRIFT This is a measure of the change in Gain Error with changes in temperature expressed in (ppm of full-scale range)/°C. DC POWER-SUPPLY REJECTION RATIO (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage ...

  • Page 11

    ... CODE Figure 7. AD5336 Typical INL Plot 0.5 0 –0.5 –1 0 1000 2000 3000 4000 CODE Figure 10. AD5336 Typical DNL Plot REF 0.5 GAIN ERROR 0 OFFSET ERROR –0.5 – 120 TEMPERATURE – C Figure 13. AD5334 Offset Error ...

  • Page 12

    ... AD5334/AD5335/AD5336/AD5344 0 0 REF 0 GAIN ERROR –0.1 –0.2 –0.3 –0.4 OFFSET ERROR –0.5 –0 – Volts DD Figure 14. Offset Error and Gain Error vs 600 500 400 300 200 100 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V – Figure 17. Supply Current vs. Supply ...

  • Page 13

    ... They operate from single supplies of 2 5.5 V and the output buffer amplifiers offer rail-to-rail output swing. The gain of the buffer amplifiers in the AD5334 and AD5336 can be set give an output voltage range ...

  • Page 14

    ... The slew rate is 0.7 V/µs with a half-scale settling time to ±0.5 LSB (at 8 bits µs with the output unloaded. See Figure 20. PARALLEL INTERFACE The AD5334, AD5336, and AD5344 load their data as a single 8-, 10-, or 12-bit word, while the AD5335 loads data as a low byte of 8 bits and a high byte containing 2 bits. ...

  • Page 15

    ... X No Data Transfer X X Clear All Registers 0 0 Load DAC A Input Register, GAIN A (AD5334/AD5336 Load DAC B Input Register, GAIN B (AD5334/AD5336 Load DAC C Input Register, GAIN C (AD5334/AD5336 Load DAC D Input Register, GAIN D (AD5334/AD5336 Update DAC Registers Table II. AD5335 Truth Table ...

  • Page 16

    ... This means that the output amplifier gain of multiple DAC devices can be controlled using a common GAIN line. The AD5336 databus must be at least 10 bits wide and is best suited to a 16-bit databus system. Examples of data formats for putting GAIN on a 16-bit databus are shown in Figure 32 ...

  • Page 17

    ... A/B is needed. DACs C and D and V REF REV. 0 AD5334/AD5335/AD5336/AD5344 used for some other purpose. The AD5336 and AD5344 have separate reference inputs for each DAC. The upper and lower limits for the test are loaded to DACs A and B which, in turn, set the limits on the CMP04 signal at ...

  • Page 18

    ... AD5334/AD5335/AD5336/AD5344 Coarse and Fine Adjustment Using the AD5334/AD5335/ AD5336/AD5344 Two of the DACs in the AD5334/AD5335/AD5336/AD5344 can be paired together to form a coarse and fine adjustment function, as shown in Figure 39. As with the window comparator previ- ously described, the description will refer to DACs A, and B and the reference connections will depend on the actual device used. ...

  • Page 19

    ... AD5306 8 4 AD5316 10 4 AD5326 12 4 AD5307 8 4 AD5317 10 4 AD5327 12 4 Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html REV. 0 AD5334/AD5335/AD5336/AD5344 Table III. Overview of AD53xx Parallel Devices Pins Settling Time Additional Pin Functions REF BUF 6 µ µs 8 µ µ µs 7 µ µ µs 6 µ ...

  • Page 20

    ... AD5334/AD5335/AD5336/AD5344 PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Thin Shrink Small Outline Package TSSOP (RU-24) 0.311 (7.90) 0.303 (7.70 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25 0.0433 (1.10) MAX 8 0.0256 (0.65) 0.0118 (0.30) 0 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.0035 (0.090) ...