ADUC824 Analog Devices, ADUC824 Datasheet - Page 41

• Manufacturer Part Number: ADUC824
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC824

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

USER INTERFACE TO OTHER ON-CHIP ADuC824
PERIPHERALS
The following section gives a brief overview of the various peripher-
als also available on-chip. A summary of the SFRs used to control
and configure these peripherals is also given.
DAC
The ADuC824 incorporates a 12-bit, voltage output DAC on-chip.
It has a rail-to-rail voltage output buffer capable of driving
DACCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
DACH/L
Function
SFR Address
Power-On Default Value
Bit Addressable
The 12-bit DAC data should be written into DACH/L right-justified such that DACL contains the lower eight bits, and the lower
nibble of DACH contains the upper four bits.
—
Name
—
—
—
DACPIN
DAC8
DACRN
DACCLR
DACEN
—
Description
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
DAC Output Pin Select
Set by user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC).
Cleared by user to direct the DAC output to Pin 3 (P1.2/DAC/IEXC1).
DAC 8-Bit Mode Bit
Set by user to enable 8-bit DAC operation. In this mode the 8-bits in DACL SFR are routed to the
8 MSBs of the DAC and the 4 LSBs of the DAC are set to zero.
Cleared by user to operate the DAC in its normal 12-bit mode of operation.
DAC Output Range Bit
Set by user to configure DAC range of 0 –AV
Cleared by user to configure DAC range 0 – 2.5 V.
DAC Clear Bit
Set to ‘1’ by user to enable normal DAC operation.
Cleared to ‘0’ by used to reset DAC data registers DAC1/H to zero.
DAC Enable Bit
Set to ‘1’ by user to enable normal DAC operation.
Cleared to ‘0’ by used to power-down the DAC.
DAC Control Register
No
DAC Data Register
DAC Data Registers, written by user to update the DAC output.
DACH (DAC Data High Byte) –>FCH
FDH
00H
DACL (DAC Data Low Byte) –>FBH
00H
No
—
Table XVI. DACCON SFR Bit Designations
DACPIN
10 kΩ/100 pF. It has two selectable ranges, 0 V to V
nal bandgap 2.5 V reference) and 0 V to AV
12-bit or 8-bit mode. The DAC has a control register, DACCON,
and two data registers, DACH/L. The DAC output can be
programmed to appear at Pin 3 or Pin 12. It should be noted
that in 12-bit mode, the DAC voltage output will be updated as
soon as the DACL data SFR has been written; therefore, the DAC
data register should be updated as DACH first followed by DACL.
–>Both Registers
–>Both Registers
DAC8
DD
.
DACRN
DACCLR
DD
ADuC824
. It can operate in
REF
DACEN
(the inter-