ADUC824 Analog Devices, ADUC824 Datasheet - Page 58

• Manufacturer Part Number: ADUC824
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC824

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

ADuC824
Mode 0: 8-Bit Shift Register Mode
Mode 0 is selected by clearing both the SM0 and SM1 bits in
the SFR SCON. Serial data enters and exits through RXD. TXD
outputs the shift clock. Eight data bits are transmitted or received.
Transmission is initiated by any instruction that writes to SBUF.
The data is shifted out of the RXD line. The eight bits are trans-
mitted with the least-significant bit (LSB) first, as shown in
Figure 40.
Reception is initiated when the receive enable bit (REN) is 1 and
the receive interrupt bit (RI) is 0. When RI is cleared the data is
clocked into the RXD line and the clock pulses are output from
the TXD line.
Mode 1: 8-Bit UART, Variable Baud Rate
Mode 1 is selected by clearing SM0 and setting SM1. Each data
byte (LSB first) is preceded by a start bit(0) and followed by a stop
bit(1). Therefore 10 bits are transmitted on TXD or received on
RXD. The baud rate is set by the Timer 1 or Timer 2 overflow
rate, or a combination of the two (one for transmission and the
other for reception).
Transmission is initiated by writing to SBUF. The ‘write to SBUF’
signal also loads a 1 (stop bit) into the ninth bit position of the
transmit shift register. The data is output bit by bit until the
stop bit appears on TXD and the transmit interrupt flag (TI) is
automatically set as shown in Figure 41.
Reception is initiated when a 1-to-0 transition is detected on
RXD. Assuming a valid start bit was detected, character reception
continues. The start bit is skipped and the eight data bits are
clocked into the serial port shift register. When all eight bits have
been clocked in, the following events occur:
if, and only if, the following conditions are met at the time the
final shift pulse is generated:
If either of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
(SHIFT CLOCK)
(SCON.1)
The eight bits in the receive shift register are latched into SBUF
The ninth bit (Stop bit) is clocked into RB8 in SCON
The Receiver interrupt flag (RI) is set
RI = 0, and
Either SM2 = 0, or SM2 = 1 and the received stop bit = 1.
(DATA OUT)
TXD
TI
CORE
RXD
CLK
ALE
TXD
START
BIT
S1
S2
D0
DATA BIT 0
MACHINE
CYCLE 1
S3
S4
D1
S5
S6
D2
S1
DATA BIT 1
D3
S2
MACHINE
CYCLE 2
S3
D4
S4
D5
MACHINE
CYCLE 7
DATA BIT 6
S4
D6
i.e. READY FOR MORE DATA
S5
S6
D7
SET INTERRUPT
S1
S2
STOP BIT
DATA BIT 7
MACHINE
CYCLE 8
S3
S4
S5
S6
Mode 2: 9-Bit UART with Fixed Baud Rate
Mode 2 is selected by setting SM0 and clearing SM1. In this
mode the UART operates in 9-bit mode with a fixed baud rate.
The baud rate is fixed at Core_Clk/64 by default, although by
setting the SMOD bit in PCON, the frequency can be doubled to
Core_Clk/32. Eleven bits are transmitted or received, a start bit(0),
eight data bits, a programmable ninth bit and a stop bit(1). The
ninth bit is most often used as a parity bit, although it can be used
for anything, including a ninth data bit if required.
To transmit, the eight data bits must be written into SBUF. The
ninth bit must be written to TB8 in SCON. When transmission is
initiated the eight data bits (from SBUF) are loaded onto the
transmit shift register (LSB first). The contents of TB8 are loaded
into the ninth bit position of the transmit shift register. The trans-
mission will start at the next valid baud rate clock. The TI flag
is set as soon as the stop bit appears on TXD.
Reception for Mode 2 is similar to that of Mode 1. The eight
data bytes are input at RXD (LSB first) and loaded onto the
receive shift register. When all eight bits have been clocked in,
the following events occur:
if, and only if, the following conditions are met at the time the
final shift pulse is generated:
If either of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
Mode 3: 9-Bit UART with Variable Baud Rate
Mode 3 is selected by setting both SM0 and SM1. In this mode
the 8051 UART serial port operates in 9-bit mode with a variable
baud rate determined by either Timer 1 or Timer 2. The opera-
tion of the 9-bit UART is the same as for Mode 2 but the baud
rate can be varied as for Mode 1.
In all four modes, transmission is initiated by any instruction that
uses SBUF as a destination register. Reception is initiated in Mode 0
by the condition RI = 0 and REN = 1. Reception is initiated in
the other modes by the incoming start bit if REN = 1.
UART Serial Port Baud Rate Generation
Mode 0 Baud Rate Generation
The baud rate in Mode 0 is fixed:
Mode 0 Baud Rate = (Core Clock Frequency /12)
Mode 2 Baud Rate Generation
The baud rate in Mode 2 depends on the value of the SMOD bit
in the PCON SFR. If SMOD = 0, the baud rate is 1/64 of the core
clock. If SMOD = 1, the baud rate is 1/32 of the core clock:
Mode 2 Baud Rate = (2
Mode 1 and 3 Baud Rate Generation
The baud rates in Modes 1 and 3 are determined by the overflow
rate in Timer 1 or Timer 2, or both (one for transmit and the
other for receive).
selected via the CD0–2 bits in the PLLCON SFR.
In these descriptions, Core Clock Frequency refers to the core clock frequency
The eight bits in the receive shift register are latched into SBUF
The ninth data bit is latched into RB8 in SCON
The Receiver interrupt flag (RI) is set
RI = 0, and
Either SM2 = 0, or SM2 = 1 and the received stop bit = 1.
SMOD
/64) × (Core Clock Frequency)