ADUC824 Analog Devices, ADUC824 Datasheet - Page 61

• Manufacturer Part Number: ADUC824
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC824

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

IEIP2
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
Interrupt Priority
The Interrupt Enable registers are written by the user to enable
individual interrupt sources, while the Interrupt Priority registers
allow the user to select one of two priority levels for each interrupt. An
interrupt of a high priority may interrupt the service routine of a low
priority interrupt, and if two interrupts of different priority occur
at the same time, the higher level interrupt will be serviced first. An
interrupt cannot be interrupted by another interrupt of the same
priority level. If two interrupts of the same priority level occur simulta-
neously, a polling sequence is observed as shown in Table XXXIII.
Source
PSMI
WDS
IE0
RDY0/RDY1
TF0
IE1
TF1
I2CI + ISPI
RI + TI
TF2 + EXF2
TII
Table XXXIII. Priority within an Interrupt Level
—
Name
—
PTI
PPSM
PSI
—
ETI
EPSM
ESI
Priority
1 (Highest)
2
3
4
5
6
7
8
9
10
11 (Lowest)
P
T
I
Watchdog Interrupt
ADC Interrupt
Description
Power Supply Monitor Interrupt
External Interrupt 0
Timer/Counter 0 Interrupt
External Interrupt 1
Timer/Counter 1 Interrupt
I
Serial Interrupt
Timer/Counter 2 Interrupt
Time Interval Counter Interrupt
2
C/SPI Interrupt
Secondary Interrupt Enable and Priority Register
A9H
A0H
No
Description
Reserved for Future Use
Written by User to Select TIC Interrupt Priority (‘1’ = High; ‘0’ = Low).
Written by User to Select Power Supply Monitor Interrupt Priority (‘1’ = High; ‘0’ = Low).
Written by User to Select SPI/I
Reserved, This Bit Must Be ‘0.’
Written by User to Enable ‘1’ or Disable ‘0’ TIC Interrupt.
Written by User to Enable ‘1’ or Disable ‘0’ Power Supply Monitor Interrupt.
Written by User to Enable ‘1’ or Disable ‘0’ SPI/I
P
P
S
M
Table XXXII. IEIP2 SFR Bit Designations
P
S
I
2
C Serial Port Interrupt Priority (‘1’ = High; ‘0’ = Low).
Interrupt Vectors
When an interrupt occurs the program counter is pushed onto the
stack and the corresponding interrupt vector address is loaded into
the program counter. The interrupt vector addresses are shown
in Table XXXIV.
Source
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
RDY0/RDY1 (ADC)
II
PSMI
TII
WDS (WDIR = 1)
The watchdog can be configured to generate an interrupt instead of a reset when it
times out. This is used for logging errors or to examine the internal status of the
microcontroller core to understand, from a software debug point of view, why a
watchdog timeout occurred. The watchdog interrupt is slightly different from the
normal interrupts in that its priority level is always set to 1 and it is not possible
to disable the interrupt via the global disable bit (EA) in the IE SFR. This is
done to ensure that the interrupt will always be responded to if a watch dog
timeout occurs. The watchdog will only produce an interrupt if the watchdog
timeout is greater than zero.
2
C + ISPI
—
Table XXXIV. Interrupt Vector Addresses
2
C Serial Port Interrupt.
E
T
I
Vector Address
0003 Hex
000B Hex
0013 Hex
001B Hex
0023 Hex
002B Hex
0033 Hex
003B Hex
0043 Hex
0053 Hex
005B Hex
E
P
S
M
ADuC824
E
S
I