ADP5020 Analog Devices, ADP5020 Datasheet - Page 19
ADP5020
Manufacturer Part Number
ADP5020
Description
Power Management Unit for Imaging Modules
Manufacturer
Analog Devices
Datasheet
1.ADP5020.pdf
(28 pages)
- Current page: 19 of 28
- Download datasheet (2Mb)
POWER-ON SEQUENCE USING THE I
When the EN pin is low, the regulator sequence is controlled by
the application processor sending I
activation. When Bit 4 (EN_ALL) in the REG_CONTROL_
STATUS register (Address 0x03) is set to 1, the regulator sequence
is as follows:
INTERNAL
XSHTDN
I
BUCK 1
BUCK 2
2
XSHTDN
C BUS
I
BUCK 1
BUCK 2
2
C BUS
LDO
VDDx
EN
POR
POR
LDO
EN
BK1_EN
V
2
UVLOR
= 1
C commands to control the
xxx_XSHTDN BITS
I
2
C SET/CLEAR
2
t
C INTERFACE
REG1
Figure 26. Individual Activation Through I
Figure 25. Activation and Power Failure Conditions
LD0_EN
= 1
Rev. 0 | Page 19 of 28
t
BK2_EN
REG2
= 1
1.
2.
3.
This sequence can be factory programmed through fuses.
Unused regulators can also be fuse programmed to be turned
off during sequencing.
t
REG3
<50µs
FORCE_XS
Buck 1
LDO
Buck 2
2
C Commands
= 1
t
XSHTDN
FORCE_XS
= 0
BK2_EN = 0
BK1_EN,
LDO_EN,
V
UVLOF
ADP5020
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