ADP5024

Manufacturer Part NumberADP5024
DescriptionDual 3 MHz, 1200 mA Buck Regulators with One 300 mA LDO
ManufacturerAnalog Devices
ADP5024 datasheet
 


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Data Sheet
FEATURES
Main input voltage range: 2.3 V to 5.5 V
Two 1200 mA buck regulators and one 300 mA LDO
24-lead, 4 mm × 4 mm LFCSP package
Regulator accuracy: ±3%
Factory programmable or external adjustable VOUTx
3 MHz buck operation with forced PWM and automatic
PWM/PSM modes
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V
LDO: output voltage range from 0.8 V to 5.2 V
LDO: input supply voltage from 1.7 V to 5.5 V
LDO: high PSRR and low output noise
APPLICATIONS
Power for processors, ASICS, FPGAs, and RF chipsets
Portable instrumentation and medical devices
Space constrained devices
C
AVIN
0.1µF
2.3V TO
5.5V
C1
4.7µF
ON
OFF
C2
4.7µF
ON
OFF
1.7V TO
5.5V
1µF
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Regulators with One 300 mA LDO
GENERAL DESCRIPTION
The
ADP5024
tors and one low dropout (LDO) regulator in a small, 24-lead,
4 mm × 4 mm LFCSP to meet demanding performance and
board space requirements.
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set high, the buck regulators operate in
forced PWM mode. When the MODE pin is set low, the buck
regulators operate in PWM mode when the load current is above
a predefined threshold. When the load current falls below a pre-
defined threshold, the regulator operates in power save mode
(PSM), improving the light load efficiency.
The two bucks operate out of phase to reduce the input capacitor
requirement. The low quiescent current, low dropout voltage, and
wide input voltage range of the LDO extends the battery life of
portable devices. The
rejection greater than 60 dB for frequencies as high as 10 kHz
while operating with a low headroom voltage.
Regulators in the
enable pins. The default output voltages can be either externally
set in the adjustable version or factory programmable to a wide
range of preset values in the fixed voltage version.
TYPICAL APPLICATION CIRCUIT
AVIN
HOUSEKEEPING
VIN1
BUCK1
EN1
EN1
MODE
VIN2
MODE
BUCK2
EN2
EN2
EN3
EN3
LDO
VIN3
(ANALOG)
C3
ADP5024
AGND
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Dual 3 MHz, 1200 mA Buck
ADP5024
combines two high performance buck regula-
ADP5024
LDO maintains power supply
ADP5024
are activated though dedicated
VOUT1
L1 1µH
SW1
V
AT
OUT1
1200mA
R1
FB1
C5
R2
10µF
PGND1
PWM
MODE
PSM/PWM
VOUT2
L2 1µH
SW2
V
AT
OUT2
1200mA
R3
FB2
C6
R4
10µF
PGND2
VOUT3
V
AT
OUT3
300mA
R5
FB3
C7
1µF
R6
©2011-2012 Analog Devices, Inc. All rights reserved.
www.analog.com

ADP5024 Summary of contents

  • Page 1

    ... AGND Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 Dual 3 MHz, 1200 mA Buck ADP5024 combines two high performance buck regula- ADP5024 LDO maintains power supply ADP5024 are activated though dedicated VOUT1 L1 1µH SW1 V AT OUT1 1200mA R1 ...

  • Page 2

    ... ADP5024 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Typical Application Circuit ............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 General Specifications ................................................................. 3 BUCK1 and BUCK2 Specifications ........................................... 4 LDO Specifications ...................................................................... 5 Input and Output Capacitor, Recommended Specifications .. 6 Absolute Maximum Ratings ............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ............................................. 9 REVISION HISTORY 1/1 — ...

  • Page 3

    ... T = −40°C to +85°C SHUTDOWN J UVLO VIN1RISE UVLO VIN1FALL UVLO VIN1RISE UVLO VIN1FALL to VOUT1, VOUT2, and VOUT3 reaching 90% of their nominal levels. Start-up times are AVIN Rev Page ADP5024 = 25°C for A Min Typ Max Unit 2.3 5.5 V 150 °C 20 °C 250 µs 300 µ ...

  • Page 4

    ... ADP5024 BUCK1 AND BUCK2 SPECIFICATIONS 2 5 −40°C to +125°C for minimum/maximum specifications, and T AVIN IN1 IN2 J specifications, unless otherwise noted. 1 Table 2. Parameter Symbol OUTPUT CHARACTERISTICS Output Voltage Accuracy ΔV /V OUT1 ΔV /V OUT2 Line Regulation (ΔV OUT1 (ΔV OUT2 Load Regulation (Δ ...

  • Page 5

    ... J 1 Min Typ 1 165 53 −3 −0.03 0.001 0.485 0 100 180 335 600 600 = 2.8 V 100 OUT3 = ADP5024 Max Unit 5 µA 100 µA 245 µA µ +0.03 %/V 0.003 %/mA 0.515 V mV 140 Ω µV rms ...

  • Page 6

    ... ADP5024 INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS T = −40°C to +125°C, unless otherwise specified. A Table 4. Parameter NOMINAL INPUT AND OUTPUT CAPACITOR RATINGS BUCK1, BUCK2 Input Capacitor Ratings BUCK1, BUCK2 Output Capacitor Ratings LDO 1 Input and Output Capacitor Ratings CAPACITOR ESR 1 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended ...

  • Page 7

    ... V to +0.3 V Package Type −0 (AVIN + 0.3 V) 24-Lead, 0.5 mm pitch LFCSP −0 (VIN3 + 0.3 V) −0 (VIN1 + 0.3 V) ESD CAUTION −0 (VIN2 + 0.3 V) −65°C to +150°C −40°C to +125°C JEDEC J-STD-020 Rev Page ADP5024 θ θ Unit °C/W ...

  • Page 8

    ... Analog Ground. 24 AGND Analog Ground. EPAD (EP) Exposed Pad recommended that the exposed pad be soldered to the ground plane. ADP5024 TOP VIEW NOTES CONNECT. DO NOT CONNECT TO THIS PIN RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE GROUND PLANE. Figure 2. Pin Configuration—View from Top of the Die Rev ...

  • Page 9

    ... Rev Page 3.6V, +25° 3.6V, +85° 3.6V, –40° 0.2 0.4 0.6 0.8 1.0 I (A) OUT Automatic Mode V = 3.6V, +25° 3.6V, +85° 3.6V, –40° 0.2 0.4 0.6 0.8 I (A) OUT Automatic Mode V = 3.6V, +85° 3.6V, +25° 3.6V, –40° 0.2 0.4 0.6 0.8 I (A) OUT PWM Mode ADP5024 1.2 = 3.3 V, OUT1 1.0 1.2 = 1.8 V, OUT2 1.0 1.2 = 0.8 V, OUT1 ...

  • Page 10

    ... ADP5024 100 0.0001 0.001 0.01 I (A) OUT Figure 9. BUCK1 Efficiency vs. Load Current, Across Input Voltage 3.3 V, Automatic Mode OUT1 100 3. 4. 0.001 0.01 I (A) OUT Figure 10. BUCK1 Efficiency vs. Load Current, Across Input Voltage ...

  • Page 11

    ... CH2 500mA Ω CH1 50mV M 4.00µs A CH2 CH4 2.00V T 28.40 mA, Automatic Mode OUT1 OUT1 T VOUT CH2 500mA Ω CH1 50mV M 4.00µs A CH2 B W CH4 2.00V 28.40 mA, Automatic Mode OUT2 OUT2 ADP5024 1.0 1.2 240mA 220mA ...

  • Page 12

    ... ADP5024 T VOUT CH2 500mA Ω CH1 50mV M 400ns B W CH4 2.00V 28.40% Figure 21. Typical Waveforms 3 OUT1 T VOUT CH2 500mA Ω CH1 50mV M 400ns B W CH4 2.00V 28.40% Figure 22. Typical Waveforms 1 OUT2 T VIN VOUT ...

  • Page 13

    ... CH3 5.00V 11.20% Figure 30. LDO Startup 3 OUT3 OUT3 0.05 0.10 0.15 0.20 I (A) OUT 400 350 300 +125°C 250 +25°C 200 150 –40°C 100 50 0 2.3 2.8 3.3 3.8 4.3 INPUT VOLTAGE (V) Figure 32. NMOS RDS vs. Input Voltage Across Temperature ON ADP5024 2. 3.3V IN 0.25 0.30 = 2.8 V OUT3 4.8 5.3 ...

  • Page 14

    ... ADP5024 250 200 150 –40°C 100 50 0 2.3 2.8 3.3 3.8 4.3 INPUT VOLTAGE (V) Figure 33. PMOS RDS vs. Input Voltage Across Temperature ON 3.45 3.40 3. 4.2V, +85° 4.2V, +25° 4.2V, –40°C IN 3.20 3.15 0 0.05 0.10 0.15 I (A) OUT Figure 34. LDO Load Regulation Across Temperature 10mA I = 100µA OUT OUT I = 1mA 2.5 OUT ...

  • Page 15

    ... FREQUENCY (Hz IN3 0 100µA 1mA –10 10mA 50mA –20 100mA 150mA –30 –40 –50 –60 –70 –80 –90 10 100 1k 10k 100k FREQUENCY (Hz IN3 ADP5024 1M 10M = 3.0 V OUT3 1M 10M = 2.8 V OUT3 1M 10M = 3.0 V OUT3 ...

  • Page 16

    ... BUCK1 CURRENT SW1 DRIVER AND ANTISHOOT THROUGH PGND1 EN1 ENBK1 ENABLE AND EN2 ENBK2 MODE EN3 CONTROL ENLDO AVIN ADP5024 VIN3 VOUT1 FB1 FB2 VOUT2 ENBK1 75Ω 75Ω AMP SOFT START SOFT START PSM COMP OSCILLATOR SYSTEM UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN ...

  • Page 17

    ... A logic level high applied to the ENx pin activates a regulator whereas a logic level low turns off a regulator. Figure 46 shows the regulator activation timings for the ADP5024 when all enable pins are connected to AVIN. Also shown is the active pull-down activation. Rev Page ADP5024 is approx- POR ...

  • Page 18

    ... ADP5024 AVIN VOUT1 VOUT3 30µs (MIN) VOUT2 50µs (MIN) BUCK1, LDO PULL-DOWNS BUCK2 PULL-DOWN V UVLO Figure 46. Regulator Sequencing ( EN1 = EN2 = EN3 Rev Page Data Sheet V POR 30µs (MIN) 50µs (MIN AVIN ...

  • Page 19

    ... PFET switch on 100% of the time, the output voltage drops below the Rev Page ADP5024 has a dedicated MODE pin controlling the PSM ensures that both bucks operate at the same ADP5024 ensures that when both bucks are in ...

  • Page 20

    ... Figure 46 shows the activation timings for the active pull- downs during regulator activation and deactivation. LDO The ADP5024 contains one LDO with low quiescent current and low dropout voltage and provides up to 300 mA of output current. Drawing a low 10 μA quiescent current (typical load makes the LDO ideal for battery-operated portable equipment ...

  • Page 21

    ... Figure 49. Capacitance vs. Voltage Characteristic Dimensions (mm) 2.0 × 1.6 × 0.9 3.2 × 2.5 × 1.6 3.2 × 2.5 × 2.5 4.0 × 4.0 × 2.1 1.9 × 2.0 × 1.0 2.5 × 2.0 × 1.2 Rev Page ADP5024 × (1 − TEMPCO) × (1 − TOL) is 9.2 μ shown in Figure 49. OUT BIAS VOLTAGE (V) I (mA) DCR (mΩ ...

  • Page 22

    ... MODE SW2 C2 4.7µF BUCK2 FB2 EN2 EN2 PGND2 ON OFF EN3 VOUT3 EN3 LDO FB3 VIN3 (ANALOG) C3 1µF ADP5024 AGND Rev Page Data Sheet Case Type Model Size X5R GRM188R60J106 0603 X5R C1608JB0J106K 0603 X5R ECJ1VB0J106M 0603 Case Type Model ...

  • Page 23

    ... Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP5024 imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. ...

  • Page 24

    ... The inductor losses are external to the device and they do not have any effect on the die temperature. The inductor losses are estimated (without core losses) by ADP5024 operates where: ADP5024 is given by DCR I OUT1(RMS) (1) where r is the normalized inductor ripple current. where the inductance ...

  • Page 25

    ... RISE FALL switching node, SW. For the ADP5024, the rise and fall times of SW are in the order of 5 ns. If the preceding equations and parameters are used for estimating the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers ...

  • Page 26

    ... ADP5024 PCB LAYOUT GUIDELINES Poor layout can affect ADP5024 performance, causing electro- magnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines. Also, refer to User Guide UG-271. • ...

  • Page 27

    ... C7 1µF L1 1µ OUT1 1200mA 10µF PWM PSM/PWM L2 1µ OUT2 1200mA 10µ OUT3 300mA R5 C7 1µF R6 Package or Dimension (mm) 0402 0402 0402 0603 0603 2.0 × 1.6 × 0.9 2.0 × 2.0 × 1.4 2.5 × 2.0 × 1.2 24-lead LFCSP ADP5024 ...

  • Page 28

    ... FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 4 Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board for ADP5024ACPZ-R7 Data Sheet Package Option CP-24-10 CP-24-10 ...