LMC835N

Manufacturer Part NumberLMC835N
DescriptionIC GRAPHIC EQUALIZER DGTL 28-DIP
ManufacturerNational Semiconductor
TypeEqualizer
LMC835N datasheet
 


Specifications of LMC835N

ApplicationsReceiverMounting TypeThrough Hole
Package / Case*Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names*LMC835N
LMC835
  
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Typical Applications
(Continued)
Sample Subroutine Program for Figure 14 LMC835-COP404L CPU Interface
HEX
CODE
LABEL
MNEMONICS
3F
LMC835
LBI
05
SEND
LD
22
SC
335F
OGI
4F
XAS
05
LD
07
XDS
05
LD
4F
XAS
05
LD
07
XDS
32
RC
4F
XAS
335D
OGJ
335B
OGI
4E
CBA
43
AISC
48
RET
80
JP
RAM
ADDRESS
COMMENTS
3C
DATA
GAIN DATA D4 D7
3D
DATA
GAIN DATA D0 D3
3E
DATA
BAND DATA D4 D7
3F
DATA
BAND DATA D0 D3
Application Hints
SWITCHING NOISE
The LMC835 uses CMOS analog switches that have small
leakages (less than 50 nA) When a band is selected for flat
gain all the switches in that band are open and the resona-
tor circuit is not connected to the LMC835 resistor network
It is only in the flat mode that the small leakage currents can
cause problems The input to the resonator circuit is usually
a capacitor and the leakage currents will slowly charge up
this capacitor to a large voltage if there is no resistive path
to limit it When the band is set to any value other than flat
the charge on the capacitor will be discharged by the resis-
tor network and there will be a transient at the output To
limit the size of this transient R
is necessary
LEAK
HOW TO AVOID SWITCHING NOISE DUE TO LEAKAGE
CURRENT (Refer to Figures 7 and 8 )
To avoid switching noise due to leakage currents when
changing the gain it is recommended to put R
k
between Pin 3 and Pin 5 11 each Pin 26 and Pin 12
24 each The resistor limits the voltage that the capacitor
can charge to with minimal effects on the equalization The
frequency response change due to R
are shown in Fig-
LEAK
ure 15 The gain error is only 0 2 dB and Q error is only 5%
at 12 dB boost or cut
COMMENTS
3F
POINT TO RAMADDRESS 3F
RAMDATA TO A
SET CARRY
SET PORT G 1111 OPEN THE AND GATES
SWAP A AND SIO CLOCK START
RAMDATA TO A MAKE SURE A
SWAP A AND RAMDATA RAMADDRESS RAMADDRESS 1
RAMDATA TO A
SWAP A AND SIO
RAMDATA TO A MAKE SURE A NEWDATA
SWAP A AND RAMDATA RAMADDRESS RAMADDRESS 1
RESET CARRY
SWAP A AND SIO CLOCK STOP
13
SET PORT G 1101 MAKE STROBE LOW
11
SET PORT G 1011 MAKE STROBE HIGH CLOSE THE
BD TO A
3
RAMADDRESS
3C THEN RETURN
k
SEND
SIMPLE WORD GENERATOR (Figure 6)
Circuit operation revolves around an MM74HC165 parallel-
in serial-out shift register Data bits D0 through D7 are ap-
plied to the parallel of the MM74HC165 from 8 toggle
switches The bits are shifted out to the DATA input of the
LMC835 in sync with the clock When all data bits have
been loaded CLOCK is inhibited and a STROBE pulse is
generated this sequence is initiated by a START pulse
LMC835-COP404L CPU INTERFACE (Refer to Figure 14 )
The diagram shows AND gates between the COP and the
LMC835 These permit G2 to inhibit the CLOCK and DATA
lines (SK and SO) during a STROBE (G1) pulse This func-
tion may also be implemented in software As shown in Fig-
ure 2 the data groups are shifted in D0 first Data is loaded
on positive clock edges
POWER SUPPLIES
100
e
LEAK
These applications show LM317 337 regulators for the
7 5V supplies for the LMC835 Since the latter draws only
g
5 mA max 1k series dropping resistors from the
amp supply and a pair of 7 5V zeners and bypass caps will
also suffice
14
DATA
GATES
15V op
g