LT1016IS8 Linear Technology, LT1016IS8 Datasheet - Page 11

• Manufacturer Part Number: LT1016IS8
• Description: IC COMPARATOR 10NS HI-SPD 8-SOIC
• Manufacturer: Linear Technology
• Series: UltraFast™r
• Type: General Purposer

Specifications of LT1016IS8

• Number Of Elements: 1
• Output Type: CMOS, Complementary, TTL
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
“Fuzz” on the edges is the difficulty in Figure 10. This
condition appears similar to Figure 10, but the oscillation
is more stubborn and persists well after the output has
gone low. This condition is due to stray capacitive feed-
back from the outputs to the inputs. A 3kW input source
impedance and 3pF of stray feedback allowed this oscilla-
tion. The solution for this condition is not too difficult.
Keep source impedances as low as possible, preferably 1k
or less. Route output and input pins and components away
from each other.
The opposite of stray-caused oscillations appears in
Figure 11. Here, the output response (Trace B) badly lags
the input (Trace A). This is due to some combination of
high source impedance and stray capacitance to ground at
the input. The resulting RC forces a lagged response at the
input and output delay occurs. An RC combination of 2k
TRACE A
TRACE B
2V/DIV
2V/DIV
Figure 11. Stray 5pF Capacitance from
Input to Ground Causes Delay
U
U
10ns/DIV
W
2V/DIV
Figure 10. 3pF Stray Capacitive Feedback
with 3kW Source Can Cause Oscillation
1016 F11
U
50ns/DIV
source resistance and 10pF to ground gives a 20ns time
constant—significantly longer than the LT1016’s
response time. Keep source impedances low and mini-
mize stray input capacitance to ground.
Figure 12 shows another capacitance related problem.
Here the output does not oscillate, but the transitions are
discontinuous and relatively slow. The villain of this
situation is a large output load capacitance. This could be
caused by cable driving, excessive output lead length or
the input characteristics of the circuit being driven. In
most situations this is undesirable and may be eliminated
by buffering heavy capacitive loads. In a few circum-
stances it may not affect overall circuit operation and is
tolerable. Consider the comparator’s output load
characteristics and their potential effect on the circuit. If
necessary, buffer the load.
Figure 12. Excessive Load Capacitance Forces Edge Distortion
2V/DIV
1016 F10
100ns/DIV
LT1016
1016 F12
11