DS80CH11 Maxim, DS80CH11 Datasheet - Page 58

• Manufacturer Part Number: DS80CH11
• Description: The system energy manager is a highly integrated microcontroller that provides several key features for systems including key scanning and control, battery and power management, as well as two 2-Wire serial I/O Ports
• Manufacturer: Maxim

KST7–KST4, KST2/P1ST7–4, P1ST2,
P2ST7–4, P2ST2–Keyboard / Power Mgr. #1
and #2 Status.
KST7–4, KST2, P1ST7–4, P1ST2, P2ST7–4, P2ST2
bits are RAM locations which can be used to communi-
cate user–defined status conditions to the host system.
They are read/write by the microcontroller and read–
only by the host CPU. The KST7–4 bits are traditionally
used by the keyboard control firmware for parity error,
receive timeout, transmit timeout, and inhibit switch sta-
tus. All of these bits are unaffected by any type of reset.
KC/D / PC/D1/PC/D2 – Keyboard / Power
Mgr.#1 and #2 Command / Data.
KC/D and PC/D1 and PC/D2 each specify whether the
associated input data register contains data or a com-
mand (0 = data, 1 = command). During a host write
operation, the associated C/D bit will be set to a 1 if A0 =
1 or will be cleared to 0 if A0 = 0. KC/D, PC/D1 and
PC/D2 are read–only status bits to both the SEM and
the host CPU. They cannot be written directly, they only
can be written as a result of the host write operation
described above. All of these bits are unaffected by any
type of reset.
KIBF / PIBF1/PIBF2 – Keyboard / Power Mgr.
#1 and #2 Input Buffer Full.
The KIBF, PIBF1 or PIBF2 flag is set to 1 whenever the
host system writes data into the associated input data
9.5 KBDOUT / PMDOUT1/PMDOUT2 – OUTPUT DATA REGISTERS
KBDOUT; SFR ADDR.=0AFH
PMDOUT1; SFR ADDR.=0BFH
PMDOUT2; SFR ADDR.=0F7H
Read/Write Access: Unrestricted.
Initialization: Undefined on any type of reset
The output data registers can be read or written by the
SEM but are read only to the host When the SEM writes
to one of the output data registers, the associated output
DS80CH11
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BIT 7
BIT 7
BIT 7
BIT 6
BIT 6
BIT 6
BIT 5
BIT 5
BIT 5
BIT 4
BIT 4
BIT 4
register. These flags also serve as interrupt pending
flags. A Keyboard Buffer Interrupt (KBI) will be gener-
ated if the Keyboard Buffer Interrupt Enable (EKB) bit is
set. Likewise, a Power Management #1 Buffer Interrupt
(PBI1) will be generated if the Power Management #1
Buffer Interrupt Enable (EPB1) is set and a power man-
agement #2 Buffer Interrupt (PBI2) will be generated if
the Power Management #2 Buffer Interrupt Enable
(EPB2) is set. All of these bits are automatically cleared
to 0 following a read of the associated input data regis-
ters. In addition, all bits are cleared to 0 following any
type of reset.
KOBF / POBF1/POBF2 – Keyboard / Power
Mgr. #1 and #2 Output Buffer Full.
KOBF, POBF1 and POBF2 are read–only status bits
which are set to 1 when the associated output data
buffer register is written by the SEM. Each of these bits
are automatically cleared to 0 when the host system
reads the associated output data registers. When the
KOBF flag is set, an active high interrupt signal to the
host will be generated through the KBOBF pin and will
remain active until the output buffer is read by the host.
Similarly, when POBF1 flag is set, an active low interrupt
signal will be issued to the host via the SMI1 pin and
when POBF2 flag is set, an active low interrupt signal
will be issued to the host via the SMI2 pin. There are no
output buffer–related interrupts to the SEM. All of these
bits are cleared to 0 following any type of reset.
buffer full flag will be set to alert the host that the output
data is available.
The contents of the output data registers are unaffected
by any type of reset.
BIT 3
BIT 3
BIT 3
BIT 2
BIT 2
BIT 2
BIT 1
BIT 1
BIT 1
BIT 0
BIT 0
BIT 0