DS80CH11 Maxim, DS80CH11 Datasheet - Page 9

• Manufacturer Part Number: DS80CH11
• Description: The system energy manager is a highly integrated microcontroller that provides several key features for systems including key scanning and control, battery and power management, as well as two 2-Wire serial I/O Ports
• Manufacturer: Maxim

2.1 PIN FUNCTION SUMMARY
PIN
106
108
121
122
123
124
125
126
127
128
117
36
43
46
17
35
86
47
68
38
37
42
40
56
57
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
SYMBOL
KBOBF
AGND
HGND
HVCC
AVCC
KBCS
GND
IOW
ALE
IOR
NC
A0
Command / Data Select: Input. Address input used by the host processor in data
transfers to the keyboard controller and power management #1 and #2 interface ports to
indicate whether the transfer is command (A0=1) or data (A0=0).
Analog Ground.
Address Latch Enable: Output. This signal functions as a clock to latch the external
address LSB from the multiplexed address/data bus on Port 0. This signal is commonly
connected to the latch enable of an external 373 family transparent latch. ALE has a
pulse width of 1.5 XTAL1 cycles and a period of 4 XTAL1 cycles. ALE is forced high
when the SEM is in a Reset condition.
Analog VCC.
Digital circuit ground.
Host Interface Ground:
Host Interface VCC:
I/O Read: Input. I/O Read is used to signal a read operation is in effect on the host
address/data bus.
I/O Write: Input. I/O Write is used to signal a write operation is in effect on the host
address/data bus.
Keyboard Chip Select: (Input, active low). This is a chip select signal used to enable
the keyboard control host interface port.
Keyboard Output Buffer Full: (Output, active high). This signal is set when the key-
board control host interface data buffer contains data to be read by the host. KBOBF will
be driven low when host reads the keyboard control data buffer register.
No Connection.
Port 0 / Address/Data Outputs 7–0: I/O. Port 0 is an open–drain 8–bit bi–directional
I/O port. As an alternate function Port 0 can function as the multiplexed address/data
bus to access off–chip memory. During the time when ALE is high, the LSB of a memory
address is presented. When ALE falls to a logic 0, the port transitions to a bi–directional
data bus. This bus is used to read external ROM and read/write external RAM memory
or peripherals. When used as a memory bus, the port provides active high drivers. The
reset condition of Port 0 is tri–state. Pull–up resistors are required when using Port 0 as
an I/O port.
DESCRIPTION
011200 9/88
DS80CH11