DS80CH11 Maxim, DS80CH11 Datasheet - Page 68

• Manufacturer Part Number: DS80CH11
• Description: The system energy manager is a highly integrated microcontroller that provides several key features for systems including key scanning and control, battery and power management, as well as two 2-Wire serial I/O Ports
• Manufacturer: Maxim

are minor restrictions on accessing the clock selection
bits. The processor must be running in a 4 clock state to
select either 64 (Slow Clock Mode1) or 1024 (Slow
Clock Mode2) clocks. This means software cannot go
directly from divide–by–64 to divide–by–1024 or vise
versa. It must return to a 4 clock rate first.
12.2.1.4 Switchback
To return to a 4 clock rate from Slow Clock Mode, soft-
ware can simply select the CD1 & CD0 clock control bits
to the 4 clocks per cycle state. However, the SEM pro-
vides several hardware alternatives for automatic
Switchback. If Switchback is enabled, then the SEM will
automatically return to a 4 clock per cycle speed when
an interrupt occurs from an enabled, valid external inter-
rupt source. A Switchback will also occur when the
serial port detects the beginning of a serial start bit if the
serial receiver is enabled. Note the beginning of a start
bit does not generate an interrupt; this occurs on recep-
tion of a complete serial word. The automatic Switch-
back on detection of a start bit allows hardware to cor-
rect baud rates in time for a proper serial reception.
Switchback is enabled by setting the SWB bit (PMR.5)
to a 1 in software. For an external interrupt, Switchback
will occur only if the interrupt source could really gener-
ate the interrupt. For example, if INT0 is enabled but has
a low priority setting, then Switchback will not occur on
INT0 if the CPU is servicing a high priority interrupt. A
serial Switchback will occur only if the serial receiver
function is enabled (REN=1, SCON0.4).
When SWB = 1, the user software will not be able to
select a reduced clock mode if the UART is active. For
example, the processor will prohibit the Slow Clock
Mode by not allowing a write to CD1 and CD0 if a serial
start bit arrived and SWB = 1. Since the reception of a
serial start bit or an interrupt priority lockout is normally
undetectable by software in an 8051, the Status register
features several new flags that are useful. These are
described below.
12.2.1.5 Status
Information in the Status register assists decisions
about switching into Slow Clock Mode. This register
contains information about the level of active interrupts
and the activity on the serial ports.
The SEM supports three levels of interrupt priority.
These levels are Power–fail, High, and Low.
DS80CH11
011200 68/88
Bits
STATUS.7–5 indicate the service status of each level. If
PIP (Power–fail Interrupt Priority; STATUS.7) is a 1,
then the processor is servicing this level. If either HIP
(High Interrupt Priority; STATUS.6) or LIP (Low Interrupt
Priority; STATUS.5) is high, then the corresponding
level is in service.
Software should not rely on a lower priority level inter-
rupt source to remove Slow Clock Mode (Switchback)
when a higher level is in service. Check the current
priority service level before entering Slow Clock Mode.
If the current service level locks out a desired Switch-
back source, then it would be advisable to wait until this
condition clears before entering Slow Clock Mode.
Alternately, software can prevent an undesired exit from
Slow Clock Mode by entering a low priority interrupt ser-
vice level before entering Slow Clock Mode. This will
prevent other low priority interrupts from causing a
Switchback.
Status also contains information about the state of the
serial port. Serial Port Zero Receive Activity (SPRA0;
STATUS.0) indicates a serial word is being received on
Serial Port 0 when this bit is set to a 1. Serial Port Zero
Transmit Activity (SPTA0; STATUS.1) indicates that the
serial port is still shifting out a serial transmission. While
one of these bits is set, hardware prohibits software
from entering Slow Clock Mode (CD1 & CD0 are write
protected) since this would corrupt the corresponding
serial transmissions.
12.2.1.6 Crystal / Ring Operation
The SEM allows software to choose the clock source as
an independent selection from the instruction cycle rate.
The user can select crystal–based or ring oscillator–
based operation under software control. Power–on
reset default is the crystal (or external clock) source.
The ring may save power depending on the actual crys-
tal speed. To save still more power, software can then
disable the crystal amplifier. This process requires two
steps. Reversing the process also requires two steps.
The XT/RG bit (EXIF.3) selects the crystal or ring as the
clock source. Setting XT/RG = 1 selects the crystal.
Setting XT/RG = 0 selects the ring. The RGMD (EXIF.2)
bit serves as a status bit by indicating the active clock
source. RGMD = 0 indicates the CPU is running from
the crystal. RGMD = 1 indicates it is running from the
ring. When operating from the ring, disable the crystal