ADV7160KS170 Analog Devices Inc, ADV7160KS170 Datasheet - Page 43

• Manufacturer Part Number: ADV7160KS170
• Description: IC DAC VIDEO COLOR 96BIT 160MQFP
• Manufacturer: Analog Devices Inc
• Type: Video DACr

Specifications of ADV7160KS170

• Rohs Status: RoHS non-compliant
• Applications: HDTV
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP

REV. 0
PAGE INDEX
Topic
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 1 & 15
ADV7160/ADV7162 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
ADV7160/ADV7162 SPECIFICATIONS . . . . . . . . . . . . . . . . . 2
ADV7160/ADV7162 TIMING CHARACTERISTICS . . . . . 3-5
TIMING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . 11
PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . 13-14
CIRCUIT DETAILS AND OPERATION . . . . . . . . . . . . . . . . 15
PIXEL PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
CLOCK CONTROL CIRCUIT . . . . . . . . . . . . . . . . . . . . . 16-17
CLOCK CONTROL SIGNALS . . . . . . . . . . . . . . . . . . . . . 17-18
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
COLOR VIDEO MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PIXEL PORT MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . 19-21
MULTIPLEXING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22
MPU PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
INTERNAL REGISTER CONFIGURATION . . . . . . . . . . . . 23
COLOR PALETTE ACCESS . . . . . . . . . . . . . . . . . . . . . . 24-25
ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DACS & VIDEO OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . 32-33
APPENDIX 1
APPENDIX 2
APPENDIX 3
APPENDIX 4
APPENDIX 5
APPENDIX 6
APPENDIX 7
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CURSOR DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 31-32
Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Pixel Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Command Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Command Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Command Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-29
Command Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-30
Command Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PLL Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PLL R Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PLL V Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Cursor X-Low and X-High Register . . . . . . . . . . . . . . . . . . . 31
Cursor Y-Low & Y-High Register . . . . . . . . . . . . . . . . . . . . . 31
Cursor Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Cursor Y Coordinate Even . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Cursor Y Coordinate Odd . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Cursor Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 31–32
Board Design and Layout Considerations . . . . . . . . . . . . 34-35
Typical Frame Buffer Interface . . . . . . . . . . . . . . . . . . . . . . . 36
10-Bit DACs and Gamma Correction . . . . . . . . . . . . . . . . . . 37
Initialization and Programming . . . . . . . . . . . . . . . . . . . . 38-39
Signature Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
JTAG Test Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Thermal and Environmental Considerations . . . . . . . . . . . . . 42
Page
–43–
FIGURE INDEX
Figure Title
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Load Circuit for Data-Bus Access &Relinquish Times
JTAG Port Timing
LOADOUT vs. Pixel Clock Input
LOADIN vs. Pixel Input Data
Pixel Input to Analog Output Pipeline with Minimum
LOADOUT to LOADIN Delay (8:1 Mode)
Pixel Input to Analog Output Pipeline with Maximum
LOADOUT to LOADIN Delay (8:1 Mode)
Pixel Input to Analog Output Pipeline with Minimum
LOADOUT to LOADIN Delay (4:1 Mode)
Pixel Input to Analog Output Pipeline with Maximum
LOADOUT to LOADIN Delay (4:1 Mode)
Pixel Input to Analog Output Pipeline with Minimum
LOADOUT to LOADIN Delay (2:1 Mode)
Pixel Input to Analog Output Pipeline with Maximum
LOADOUT to LOADIN Delay (2:1 Mode)
Pixel Clock Input vs. Programmable Clock Output
SCKIN vs. SCKOUT
Analog Output Response vs, Pixel Clock
MPU Timing
Multiplexed Color Inputs
Clock Control Circuit
LOADOUT vs. Pixel Clock
SCKOUT Generation Circuit
Interface Using SCKIN and SCKOUT
PLL Block Diagram
PLL Transfer Function
PLL Jitter
24-Bit to 30-Bit True Color Configuration
15-Bit to 24-Bit True Color Configuration
8-Bit to 30-Bit Pseudo Color Configuration
16-Bit Tue Color Mapping Using R7–R0 and G7–G0
15-Bit True Color Mapping Using R7–R3, G7–G3 and
B7–B3
15-Bit True Color Mapping Using R6–R0 and G7–G0
16-Bit True Color (Bypass) Using R7–R0 and G7–G0
15-Bit True Color (Bypass) Using R6–R0 and G7–G0
Direct Interfacing of Video Memory
8-Bit Pseudo Color in 8:1 Multiplexing Mode
MPU Port and Register Configuration
Internal Register Configuration and Address Decoding
8-Bit Databus Using 10-Bit DACs
8-Bit Databus Using 8-Bit DACs
10-Bit Databus Using 10-Bit DACs
10-Bit Databus Using 8-Bit DACs
Mode Register 1
Command Register 1
Command Register 2
Command Register 3
Command Register 4
PLL Command Register
Cursor Control Register
DAC Output Termination
Composite Video Waveform, SYNC decoded;
Pedestal = 7.5 IRE; DAC Gain = 3996
Composite Video Waveform, SYNC decoded;
Pedestal = 0 IRE; DAC Gain = 4224
Composite Video Waveform, SYNC & TRISYNC
Composite Video Waveform, Pedestal = 0 IRE;
DAC Gain = 4311
decoded; Pedestal = 7.5 IRE; DAC Gain = 5592
ADV7160/ADV7162