74HCT125D,652 NXP Semiconductors, 74HCT125D,652 Datasheet - Page 13

• Manufacturer Part Number: 74HCT125D,652
• Description: IC BUFFER DVR TRI-ST QD 14SOICN
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT125D,652

• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 4
• Number Of Bits Per Element: 1
• Current - Output High, Low: 6mA, 6mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Logic Family: HCT
• Number Of Channels Per Chip: 4
• Polarity: Non-Inverting
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 6 mA
• Low Level Output Current: 6 mA
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 4 / 4
• Output Type: 3-State
• Propagation Delay Time: 25 ns at 4.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4995; 74HCT125D; 74HCT125D,652; 74HCT125D; 933757010652

Philips Semiconductors
AC waveforms 74HCT
Test circuit for 74HCT
March 1988
handbook, full pagewidth
HCMOS family characteristics
C
R
(1) In Fig.9 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals
(2) For AC measurements: t
Fig.9
L
T
(SET, RESET and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual
active levels of the forcing signals are specified in the individual device data sheet.
=
=
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
load capacitance including jig and probe capacitance (see AC
CHARACTERISTICS for values).
termination resistance should be equal to the output impedance Z
the pulse generator.
OUTPUT
PRESET
CLOCK
RESET,
r
INPUT
INPUT
INPUT
DATA
SET,
= t
f
= 6 ns; when measuring f
handbook, halfpage
GENERATOR
10%
1.3 V
PULSE
t su
t rem
1.3 V
t r
10%
1.3 V
t PLH
90%
t WH
max
Fig.10 Test circuit.
1.3 V
V I
90%
t h
, there is no constraint on t
1/f max
t TLH
t f
R T
13
t WL
o
D.U.T
V CC
t su
of
t PHL
V O
r
, t
f
with 50% duty factor.
C L
t h
FAMILY SPECIFICATIONS
t THL
MGK565
50 pF
MGK568
3 V
GND
3 V
GND
3 V
GND