74HCT125D,652 NXP Semiconductors, 74HCT125D,652 Datasheet - Page 16

IC BUFFER DVR TRI-ST QD 14SOICN

74HCT125D,652

Manufacturer Part Number
74HCT125D,652
Description
IC BUFFER DVR TRI-ST QD 14SOICN
Manufacturer
NXP Semiconductors
Series
74HCTr

Specifications of 74HCT125D,652

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
6mA, 6mA
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Logic Family
HCT
Number Of Channels Per Chip
4
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 6 mA
Low Level Output Current
6 mA
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
4 / 4
Output Type
3-State
Propagation Delay Time
25 ns at 4.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Lead Free Status / Rohs Status
 Details
Other names
568-4995
74HCT125D
74HCT125D,652
74HCT125D
933757010652
Philips Semiconductors
HCMOS family characteristics
FAMILY SPECIFICATIONS
AC CHARACTERISTICS
The “AC CHARACTERISTICS” table lists the guaranteed
limits when a device is tested under the conditions given in
the AC Test Circuits and Waveforms section.
TEST CIRCUITS
Good high-frequency wiring practices should be used in
test circuits. Capacitor leads should be as short as
possible to minimize ripples on the output waveform
transitions and undershoot. Generous ground metal
(preferably a ground-plane) should be used for the same
reasons. A V
decoupling capacitor should be provided
CC
at the test socket, also with short leads. Input signals
should have rise and fall times of 6 ns, a signal swing of
0 V to V
for 74HC and 0 V to 3 V for 74HCT; a 1.0 MHz
CC
square wave is recommended for most propagation delay
tests. The repetition rate must be increased for testing
f
. Two pulse generators are usually required for testing
max
such parameters as set-up time, hold time and removal
time. f
is also tested with 6 ns input rise and fall times,
max
with a 50% duty factor, but for typical f
as high as
max
60 MHz, there are no constraints on rise and fall times.
March 1988
16

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