TMP86xy44UG Toshiba, TMP86xy44UG Datasheet - Page 142

• Manufacturer Part Number: TMP86xy44UG
• Manufacturer: Toshiba

Specifications of TMP86xy44UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 60
• Ram Size: 1K
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: 1
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 4.5 to 5.5

12.9 Status Flag
12.9.1 Parity Error
12.9.2 Framing Error
12.9.3 Overrun Error
RXD pin
UARTSR<FERR>
INTRXD interrupt
UARTSR<PERR> is set to “1”. The UARTSR<PERR> is cleared to “0” when the RDBUF is read after read-
ing the UARTSR.
The UARTSR<FERR> is cleared to “0” when the RDBUF is read after reading the UARTSR.
Shift register
UARTSR<OERR> is set to “1”. In this case, the receive data is discarded; data in RDBUF are not affected.
The UARTSR<OERR> is cleared to “0” when the RDBUF is read after reading the UARTSR.
Shift register
RXD pin
UARTSR<PERR>
INTRXD interrupt
When parity determined using the receive data bits differs from the received parity bit, the parity error flag
When “0” is sampled as the stop bit in the receive data, framing error flag UARTSR<FERR> is set to “1”.
When all bits in the next data are received while unread data are still in RDBUF, overrun error flag
Figure 12-6 Generation of Framing Error
Figure 12-5 Generation of Parity Error
xxxx0 **
xxx0 **
Final bit
Parity
Page 131
pxxxx0
xxxx0
Stop
*
*
Stop
1pxxxx0
0xxxx0
After reading UARTSR then
RDBUF clears FERR.
After reading UARTSR then
RDBUF clears PERR.
TMP86CS44UG