TMP86xy44UG Toshiba, TMP86xy44UG Datasheet - Page 88

• Manufacturer Part Number: TMP86xy44UG
• Manufacturer: Toshiba

Specifications of TMP86xy44UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 60
• Ram Size: 1K
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: 1
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 4.5 to 5.5

8.3.6 Programmable Pulse Generate (PPG) Output Mode
formed in the internal clock. To start the timer, TC1CR<TC1S> specifies either the edge of the input pulse to
the TC1 pin or the command start. TC1CR<MPPG1> specifies whether a duty pulse is produced continuously
or not (one-shot pulse).
ative pulse can be generated. Since the inverted level of the timer F/F1 output level is output to the
specify TC1CR<TFF1> to “0” to set the high level to the
Upon reset, the timer F/F1 is initialized to “0”.
In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting per-
Since the output level of the
Note 1: To change TC1DRA or TC1DRB during a run of the timer, set a value sufficiently larger than the count value
Note 2: Do not change TC1CR<TFF1> during a run of the timer. TC1CR<TFF1> can be set correctly only at initial-
Note 3: In the PPG mode, the following relationship must be satisfied.
Note 4: Set TC1DRB after changing the mode of TC1M to the PPG mode.
• When TC1CR<MPPG1> is set to “0” (Continuous pulse generation)
• When TC1CR<MPPG1> is set to “1” (One-shot pulse generation)
of the counter. Setting a value smaller than the count value of the counter during a run of the timer may
generate a pulse different from that specified.
ization (after reset). When the timer stops during PPG, TC1CR<TFF1> can not be set correctly from this
point onward if the PPG output has the level which is inverted of the level when the timer starts. (Setting
TC1CR<TFF1> specifies the timer F/F1 to the level inverted of the programmed value.) Therefore, the
timer F/F1 needs to be initialized to ensure an arbitrary level of the PPG output. To initialize the timer F/F1,
change TC1CR<TC1M> to the timer mode (it is not required to start the timer mode), and then set the PPG
mode. Set TC1CR<TFF1> at this time.
TC1DRA > TC1DRB
level of the
ues counting. When a match between the up-counter and the TC1DRA value is detected, the level of
the
this time, and then continues counting and pulse generation.
the counter stops.
level of the
ues counting. When a match between the up-counter and the TC1DRA value is detected, the level of
the
“00” automatically at this time, and the timer stops. The pulse generated by PPG retains the same
level as that when the timer stops.
When a match between the up-counter and the TC1DRB value is detected after the timer starts, the
When TC1S is cleared to “00” during PPG output, the
When a match between the up-counter and the TC1DRB value is detected after the timer starts, the
PPG
PPG
pin is inverted and an INTTC1 interrupt request is generated. The up-counter is cleared at
pin is inverted and an INTTC1 interrupt request is generated. TC1CR<TC1S> is cleared to
PPG
PPG
pin is inverted and an INTTC1 interrupt request is generated. The up-counter contin-
pin is inverted and an INTTC1 interrupt request is generated. The up-counter contin-
PPG
pin can be set with TC1CR<TFF1> when the timer starts, a positive or neg-
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PPG
pin, and “1” to set the low level to the
PPG
pin retains the level immediately before
TMP86CS44UG
PPG
PPG
pin,
pin.