TMP86xy46NG Toshiba, TMP86xy46NG Datasheet - Page 26

• Manufacturer Part Number: TMP86xy46NG
• Manufacturer: Toshiba

Specifications of TMP86xy46NG

• Package: SDIP42
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 8/16/32
• Ram Size: 512/512/1K
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 33
• Power Supply (v): 4.5 to 5.5

System Control Register 1
System Control Register 2
SYSCR1
SYSCR2
(0038H)
(0039H)
Note 1: Always set RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM to “1” when transiting
Note 2: When STOP mode is released with
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don’t care
Note 4: Bits 1 in SYSCR1 are read as undefined data when a read instruction is executed.
Note 5: As the hardware becomes STOP mode under OUTEN = “0”, input value is fixed to “0”; therefore it may cause external
Note 6: When the key-on wakeup is used, RELM should be set to "1".
Note 7: Port P20 is used as
Note 8: The warmig-up time should be set correctly for using oscillator.
Note 1: A reset is applied if both XEN and XTEN are cleared to “0”, XEN is cleared to “0” when SYSCK = “0”, or XTEN is cleared
Note 2: *: Don’t care, TG: Timing generator, *; Don’t care
Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value.
Note 4: Do not set IDLE and TGHALT to “1” simultaneously.
Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period
Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”.
Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”.
from SLOW mode to STOP mode.
interrupt request on account of falling edge.
High-Z mode.
to “0” when SYSCK = “1”.
of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>.
STOP
TGHALT
XEN
SYSCK
OUTEN
XTEN
STOP
RELM
RETM
IDLE
7
7
XEN
WUT
RELM
XTEN
High-frequency oscillator control
Low-frequency oscillator control
Main system clock select
(Write)/main system clock moni-
tor (Read)
CPU and watchdog timer control
(IDLE1/2 and SLEEP1/2 modes)
TG control (IDLE0 and SLEEP0
modes)
6
6
STOP mode start
Release method for STOP
mode
Operating mode after STOP
mode
Port output during STOP mode
Warm-up time at releasing
STOP mode
SYSCK
STOP
RETM
5
5
pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes
OUTEN
IDLE
4
4
RESET
0: CPU core and peripherals remain active
1: CPU core and peripherals are halted (Start STOP mode)
0: Edge-sensitive release
1: Level-sensitive release
0: Return to NORMAL1/2 mode
1: Return to SLOW1 mode
0: High impedance
1: Output kept
0: Turn off oscillation
1: Turn on oscillation
0: Turn off oscillation
1: Turn on oscillation
0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2)
1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2)
0: CPU and watchdog timer remain active
1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes)
0: Feeding clock to all peripherals from TG
1: Stop feeding clock to peripherals except TBT from TG.
3
3
pin input, a return is made to NORMAL1 regardless of the RETM contents.
000
010
100
110
*01
*11
(Start IDLE0 and SLEEP0 modes)
Page 15
TGHALT
WUT
2
2
Return to NORMAL mode
3 x 2
3 x 2
3 x 2
1
1
2
2
2
16
14
10
16
14
10
/fc
/fc
/fc
/fc
/fc
/fc
0
0
(Initial value: 0000 000*)
(Initial value: 1000 *0**)
Return to SLOW mode
3 x 2
3 x 2
3 x 2
2
2
2
13
6
6
/fs
/fs
13
/fs
6
6
/fs
/fs
/fs
TMP86PM46NG
R/W
R/W
R/W
R/W
R/W
R/W
R/W