IFX 91041EJ V50 Infineon Technologies, IFX 91041EJ V50 Datasheet - Page 4

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IFX 91041EJ V50

Manufacturer Part Number
IFX 91041EJ V50
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of IFX 91041EJ V50

Packages
PG-DSO-8
Comment
VQ fixed to 5.0V; Tolerance 2% up to 1000mA; DSO-8 EP
Vq (max)
5.0 V
Iq (max)
1,800.0 mA
Iq (typ)
7,000.0 µA
Output
Buck Converter
3
3.1
Figure 2
3.2
Pin
1
2
3
4
5
6
7
8
Exposed Pad
Data Sheet
Symbol Function
SYNC
GND
COMP
FB
BDS
BUO
EN
VS
Pin Configuration
Pin Assignment
Pin Configuration
Pin Definitions and Functions
Synchronization Input.
Connect to an external clock signal in order to synchronize/adjust the switching frequency.
If not used connect to GND.
Ground.
Compensation Input.
Frequency compensation for regulation loop stability.
Connect to compensation RC-network.
Feedback Input.
For the adjustable output voltage versions (IFX91041EJV) connect via voltage divider to output
capacitor.
For the fixed voltage version (IFX91041EJV50, IFX91041EJV33) connect this pin directly to the
output capacitor.
Buck Driver Supply Input.
Connect the bootstrap capacitor between this pin and pin BUO.
Buck Switch Output.
Source of the integrated power-DMOS transistor. Connect directly to the cathode of the catch
diode and the buck circuit inductance.
Enable Input.
Active-high enable input with integrated pull down resistor.
Supply Voltage Input.
Connect to supply voltage source.
Connect to heatsink area and GND by low inductance wiring.
COMP
SYNC
GND
FB
1
2
3
4
IFX91041
4
S08_PIN.vsd
8
7
6
5
VS
EN
BUO
BDS
Rev. 1.1, 2011-07-08
Pin Configuration
IFX91041

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