CS8416 Cirrus Logic, Inc., CS8416 Datasheet
CS8416
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CS8416 Summary of contents
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... Preliminary Product Information Cirrus Logic, Inc. www.cirrus.com General Description The CS8416 is a monolithic CMOS device which re- ceives and decodes one of 8 channels of audio data according to the IEC60958, S/PDIF, EIAJ CP1201, or AES3 interface standards. The CS8416 has a serial dig- ital audio output port and comprehensive control ability through a selectable control port in Software Mode or through selectable pins in Hardware Mode ...
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... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys 2 C system. CS8416 DS578PP3 ...
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... Interrupt 1 Status (0Dh) .............................................................................................. 35 11.14. Q-Channel Subcode (0Eh - 17h) ................................................................................. 35 11.15. OMCK/RMCK Ratio (18h) ......................................................................................... 36 11.16. Channel Status Registers (19h - 22h) ......................................................................... 36 11.17. IEC61937 PC/PD Burst preamble (23h - 26h)............................................................. 36 11.18. CS8416 I.D. and Version Register (7Fh) ..................................................................... 36 12. PIN DESCRIPTION - SOFTWARE MODE ........................................................................... 37 13. HARDWARE MODE ............................................................................................................ 39 13.1. Serial Audio Port Formats ............................................................................................ 39 13.2. Hardware Mode Function Selection ............................................................................. 40 13 ...
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... Figure 25. Jitter Attenuation Characteristics of PLL ...................................................................... 52 LIST OF TABLES Table 1. Delays by Frequency Values........................................................................................... 16 Table 2. Clock Switching Output Clock Rates............................................................................... 18 Table 3. GPO Pin Configurations .................................................................................................. 19 Table 4. Hardware Mode Start Up Pin Conditions ........................................................................ 40 Table 5. Hardware Mode Serial Audio Format Select ................................................................... 41 Table 6. External PLL Component Values .................................................................................... Mode .................................................................................. 24 CS8416 DS578PP3 ...
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... VA 3.13 VD 3.13 VL 3.13 ‘-CS’ & ‘-CZ’ T -10 A ‘-IS’ & ‘-IZ’ -40 (AGND, DGND = 0V; all voltages with respect to 0V. Operation Symbol Min VA, VD,VL (Note -0 - -65 stg CS8416 Typ Max Units 3.3 3.46 V 3.3 3.46 V 3.3 or 5.0 5. +70 °C - +85 Max Units - 6 ±10 mA (VL) + 0.3 V 125 ° ...
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... DGND = 0 V; all voltages with respect to 0 V.) Symbol (AGND = DGND = 0 V; all voltages with respect to 0 V.) Symbol (Inputs: Logic Logic 1 = VL; C Symbol Min 200 30 (Note CS8416 Min Typ Max Units µ µ µ µ 5 ...
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... OLRCK (input) t lrckd OSCLK (input SDOUT Figure 2. Audio Port Slave Mode and Data Input Timing CS8416 Min Typ Max Units - - ...
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... Figure 3. SPI Mode Timing CS8416 Min Max Unit 0 6.0 MHz 1.0 - µ ...
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... Symbol f scl t buf t hdst t low t high t sust (Note 13) t hdd t sud susp Repeated Start t high t t sud t sust hdd 2 Figure Mode Timing CS8416 2 C FORMAT Min Max Unit - 100 kHz 4.7 - µs 4.0 - µs 4.7 - µs 4.0 - µs 4.7 - µ 250 - ...
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... RMCK RXP5 RXP6 OMCK RXP7 GPO0 AD0 / CS GPO1 AD1 / CDIN AD2/GPO2 SCL / CCLK SDA / CDOUT RST AGND FILT DGND R FLT C C FLT RIP *** CS8416 +3 µ 0.1 F 1nF 47k Ω Serial Audio Input Device Clock Control Clock Source External Interface DS578PP3 ...
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... SDOUT RXP1 CS8416 RXP2 RXP3 RST RXSEL0 RXSEL1 RMCK TXSEL0 TXSEL1 OMCK * NV/RERR * AUDIO 96KHZ * TX RCBL * * AGND FILT DGND R FLT C C FLT RIP **** CS8416 +3 µ 0.1 F 1nF Serial Audio Input Device 47k Ω Clock Control Clock Source External Interface 11 ...
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... The CS8416 utilizes an 8:2 multiplexer to select between eight inputs for decoding and to allow an input signal to be routed to an output of the CS8416. Input data is either differential or single-ended. A low jitter clock is recovered from the incoming data using a PLL. The decoded audio data is output through a con- figurable, 3-wire serial audio output port ...
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... When in slave mode, the serial audio output port cannot be set for right-justified data. The CS8416 allows immediate mute of the serial audio output port audio data by the MUTESAO bit of Control Register 1. ...
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... Left MSB LSB MSB Extended MSB Extended Left LSB SOSF* SORES[1:0]* SOJUST CS8416 Right LSB MSB Right MSB LSB MSB Right MSB LSB MSB Ex Right MSB SODEL* SOSPOL* SOLRPOL ...
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... AES data and the slave serial output LRCK. The CS8416 uses a hysteresis window when a slip/repeat event occurs. The slip/repeat is triggered when an edge of OLRCK passes a window size from the beginning of the Z/X preamble. Without the hysteresis window, jitter on OLRCK with a frequency very close to Fs could slip back and forth, causing multiple slip/repeat events ...
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... OLRCK (depending on the setting of SOLRPOL in register 05h) will be treated as being sampled at the same time. Since the CS8416 has no control of the OLRCK in slave mode, the latency of the data through the part will be a multiple of 1/Fs plus the delay between OLRCK and the preambles. ...
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... RXN. Single ended signals are accommodated by using the RXP[7:0] inputs and AC coupling RXN to ground. All active inputs to the CS8416 8:2 input multiplexer should be coupled through a capacitor as these in- puts are biased at VL/2 when selected. These inputs are floating when not selected. Unused multiplexer inputs should be left floating or tied to AGND. The recommended capacitor value is 0.01 µ ...
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... MHz s 256*F 12.288 MHz s 256*F 12.288 MHz s 256*F ~500 kHz s 256*F 11.2896 MHz s Table 2. Clock Switching Output Clock Rates CS8416 RMCK OSCLK OLRCK 3.072 MHz 48 kHz 3.072 MHz 48 kHz ~125 kHz ~1.95 kHz 2.8224 MHz 44.1 kHz 3.072 MHz 48 kHz 3.072 MHz ...
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... Three General Purpose Outputs (GPO) are provided to allow the equipment designer flexibility in config- uring the CS8416. Fourteen signals are available to be routed to any of the GPO pins. The outputs of the GPO pins are set through the GPOxSEL[3:0] bits in the Control2 (02h) and Control3 (03h) registers. All GPO pins default to GND after reset ...
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... ERROR AND STATUS REPORTING 7.1. General While decoding the incoming bi-phase encoded data stream, the CS8416 has the ability to identify various error conditions. 7.1.1. Software Mode Software mode allows the most flexibility in reading errors. When unmasked, bits in the Receiver Error register (0Ch) indicate the following errors: 1) QCRC – ...
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... CS8416. However, certain non-audio sources, such as AC-3 or MPEG encoders, may not adhere to this convention, and the bit may not be properly set. The CS8416 AES3 receiver can detect such non-audio data through the use of an autodetect module. The autodetect module is similar to autodetect software used in Cirrus Logic DSPs ...
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... VLRCK is a virtual work clock, available through the GPO pins, that can be used to frame the C/U output. – VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate. – If the serial audio output port is in master mode, VLRCK = OLRCK. – C/U transitions are aligned within ±1% of VLRCK period to VLRCK edges 22 Figure 10. C/U data outputs CS8416 DS578PP3 ...
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... VL or DGND as desired. The GPO2 pin is used to set the AD2 bit by connecting a 47 kΩ resistor from the GPO2 pin DGND. The state of the pin is sensed while the CS8416 is being reset. The upper 4 bits of the 7-bit address field are fixed at 0010 ...
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... SPI Format In SPI format the CS8416 chip select signal, CCLK is the Control Port bit clock, CDIN is the input data line from the microcontroller, CDOUT is the output data line and the chip address is 0010000. CS, CCLK and CDIN are all inputs and data is clocked in on the rising edge of CCLK. CDOUT is an output and is high impedance when not actively outputting data ...
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... MAP. To read multiple registers, keep CS low and continue providing clocks on CCLK. End the read transaction by setting CS high. The CDOUT line will high impedance state once CS goes high. CS CCLK CHIP ADDRESS 0010000 CDIN CDOUT Figure 13. Control Port Timing, SPI Format (Read) DS578PP3 R/W DATA MSB byte 1 CS8416 LSB byte n 25 ...
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... FRAME FRAME ORR6 ORR5 ORR4 ORR3 AC0[6] AC0[5] AC0[4] AC0[3] AC1[6] AC1[5] AC1[4] AC1[3] AC2[6] AC2[5] AC2[4] AC2[3] AC3[6] AC3[5] AC3[4] AC3[3] CS8416 TRUNC Reserved Reserved HOLD0 RMCKF CHS TXSEL2 TXSEL1 TXSEL0 SODEL SOSPOL SOLRPOL VM CONFM BIPM PARM RERRM ...
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... BC4[3] PC0[6] PC0[5] PC0[4] PC0[3] PC1[6] PC1[5] PC1[4] PC1[3] PD0[6] PD0[5] PD0[4] PD0[3] PD1[6] PD1[5] PD1[4] PD1[3] ID2 ID1 ID0 VER3 CS8416 AC4[2] AC4[1] AC4[0] BC0[2] BC0[1] BC0[0] BC1[2] BC1[1] BC1[0] BC2[2] BC2[1] BC2[0] BC3[2] BC3[1] BC3[0] BC4[2] BC4[1] BC4[0] ...
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... INT onto GPO2 in I quired on GPO2 to specify the AD2 bit of the chip address. 11 – Reserved INT0 HOLD1 2 C control port mode since an external resistor is re- CS8416 TRUNC Reserved Reserved HOLD0 RMCKF CHS DS578PP3 ...
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... Channel A. Thus it is impossible to have de-emphasis applied to one channel but not the other. The de-emphasis filter is turned off if the audio data is detected to be non-audio data. DS578PP3 . CS8416 GPO0SEL2 GPO0SEL1 GPO0SEL0 29 ...
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... Internal clocks are stopped. Internal state machines are reset. The fully static control port is operational, allowing registers to be read or changed. Power consumption is low Normal part operation. This bit must be written to the 1 state to allow the CS8416 to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1. ...
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... Default = ‘0’ MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge. DS578PP3 SORES0 SOJUST . CS8416 SODEL SOSPOL SOLRPOL 31 ...
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... Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved UNLOCKM DETCM CCHM DETC1 CCH1 DETC0 CCH0 CS8416 CONFM BIPM PARM RERRM QCHM FCHM See “General Purpose Outputs” RERR1 QCH1 FCH1 RERR0 QCH0 ...
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... Format Detect Status (0Bh PCM IEC61937 Note: PCM, DTS_LD, DTS_CD and IEC61937 are mutually exclusive. A ‘1’ indicated the condition was detected. DS578PP3 AUX0 PRO DTS_LD DTS_CD CS8416 COPY ORIG EMPH Reserved DGTL_SIL 96KHZ 33 ...
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... BIP - Bi-phase error bit. Updated on sub-frame boundaries error Bi-phase error. This indicates an error in the received bi-phase coding. PAR - Parity bit. Updated on sub-frame boundaries error Parity error UNLOCK V CS8416 CONF BIP PAR DS578PP3 ...
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... ADDRESS TRACK TRACK INDEX INDEX MINUTE MINUTE SECOND SECOND FRAME FRAME ZERO ZERO ABS MINUTE ABS MINUTE ABS SECOND ABS SECOND ABS FRAME ABS FRAME CS8416 RERR QCH FCH ADDRESS ADDRESS ADDRESS TRACK TRACK TRACK INDEX INDEX INDEX MINUTE ...
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... Burst Preamble PC Byte 1 25h Burst Preamble PD Byte 0 26h Burst Preamble PD Byte 1 11.18. CS8416 I.D. and Version Register (7Fh ID3 ID2 ID1 ID[3: code for the CS8416. Permanently set to 0010 VER[3:0] = 0001 (revision A) VER[3:0] = 0010 (revision B) VER[3:0] = 0011 (revision ORR4 ORR3 AC0[7] ...
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... RST 9 Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. ...
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... CS8416. See section 6. Control Port Interface. SCL/CCLK 16 Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and out of the CS8416. CCLK isan open drain ouput and requires an external pull-up resistor to VL. See section 6. Control Port Interface. AD0/CS 14 Address Bit 0 (I CS8416 into SPI control port mode ...
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... HARDWARE MODE The CS8416 has a hardware mode which allows the device to operate without a microcontroller. Hardware mode is selected by connecting the 47 kΩ pull-up/down resistor on the SDOUT pin to ground. Various pins change function in hardware mode, described in the Hardware Mode Function Selection. Hardware mode data flow is shown in Figure 15. Audio data is input through the AES3/SPDIF receiver, and routed to the serial audio output port ...
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... Hardware Mode Function Selection Hardware Mode and several options for Hardware Mode are selected by pulling CS8416 pins down to DGND through a 47 kΩ resistor immediately after RST is released. For each mode, every start-up option select pin MUST have an external pull-up or pull-down resistor as there are no internal pull-up or pull-down resistors for these startup conditions (set after reset) ...
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... QCRCM = 0 CRCM = 0 UNLOCKM = 1 CONFM = 1 BIPM = 1 PARM = set by NV/RERR pull-down/up at startup. Registers 07h through 7Fh do not have Hardware Mode equivalent settings. DS578PP3 SOSF SORES[1:0] SOJUST SODEL SOSPOL SOLRPOL CS8416 ...
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... RST 9 Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. ...
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... U pin is pulled down kΩ resistor to DGND when the U pin is pulled kΩ resistor to DGND the input sample rate is ≤ 48 kHz, ouputs a “0”. Outputs a “1” Output Indicates the beginning of a received channel status block. or 128*F s CS8416 at reset ...
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... The pins are then switched to be outputs. This mechanism allows output pins to be used to set alternative modes in the CS8416 by connecting a 47 kΩ resistor to between the pin and either VL (HI) or DGND (LO). For each mode, every start-up option select pin MUST have an external pull-up or pull-down resistor as there are no internal pull-up or pull-down resistors for these startup conditions ...
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... L 0.016 ∝ 0° DS578PP3 D INCHES NOM MAX 0.098 0.104 0.008 0.012 0.017 0.020 0.011 0.013 0.705 0.713 17.70 0.295 0.299 0.050 0.060 0.407 0.419 10.00 0.026 0.050 4° 8° JEDEC #: MS-013 Controlling Dimension is Millimeters CS8416 MILLIMETERS MIN NOM MAX 2.35 2.50 2.65 0.10 0.20 0.30 0.33 0.42 0.51 0.23 0.28 0.32 17.90 18.10 7.40 7.50 7.60 1.02 1.27 1.52 10.34 10.65 0.40 ...
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... SEATING PLANE SIDE VIEW MAX MIN -- 0.47 -- 0.006 0.05 0.04 0.80 0.012 0.19 0.386 BSC 9.60 BSC 0.256 6.30 0.177 4. 0.029 0.50 4° 8° 0° JEDEC #: MO-153 Controlling Dimension is Millimeters. CS8416 1 E1 END VIEW L MILLIMETERS NOTE NOM MAX -- 1.20 0.10 0.15 0.90 1.00 0.245 0.30 2,3 9.70 BSC 9.80 BSC 6.40 6.50 4.40 4.50 0.65 BSC -- 0.60 0.75 4° 8° DS578PP3 ∝ ...
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... APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS 17.1. AES3 Receiver External Components The CS8416 AES3 receiver is designed to accept both the professional and consumer interfaces. The digital audio specifications for professional use call for a balanced receiver, using XLR connectors, with 110 Ω ± 20% impedance. The XLR connector on the receiver should have female pins with a male shell. ...
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... Figure 19. S/PDIF MUX Input Circuit 0.01 µF Gate 0.01 µF Figure 20. TTL/CMOS Input Circuit CS8416 CS8416 µ 0. See Text RXP0 110 Ω µ 0.01 F RXN .0 1 µ µ µ µ F CS8416 RXP0 RXN DS578PP3 ...
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... APPENDIX B: CHANNEL STATUS BUFFER MANAGEMENT 18.1. AES3 Channel Status (C) Bit Management The CS8416 contains sufficient RAM to store the first 5 bytes of C data for both A and B channels ( bits). The user may read from this buffer’s RAM through the control port. ...
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... PLL first locks onto upon application of an bi-phase encoded data stream or after enabling the CS8416 clocks by setting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will return to its wide lock range mode and re-acquire a new nominal center sample rate. ...
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... The traces themselves are short to minimize the inductance in the filter path. The VA and AGND traces extend back to their origin and are shown only in truncated form in the drawing. DS578PP3 FLT , C FLT 1000 C pF RIP C .1µF FLT Figure 24. Recommended Layout Example CS8416 , an X7R dielectric is preferred. Avoid , C , and the 1000 pF decoupling FLT RIP 51 ...
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... Figure 25. Jitter Attenuation Characteristics of PLL FLT FLT 3 k Ω Table 6. External PLL Component Values itter F requency (Hz) CS8416 C Settling Time RIP DS578PP3 ...
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Notes • ...
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