CS8427-CS Cirrus Logic, Inc., CS8427-CS Datasheet
CS8427-CS
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CS8427-CS Summary of contents
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... AES3 stream. Target applications include A/V receivers, CD-R, DVD receivers, multimedia speakers, digital mixing consoles, effects processors, set-top boxes, and computer and au- tomotive audio systems. ORDERING INFORMATION CS8427-CS CS8427-CSZ, Lead Free 28-pin SOIC CS8427-CZ CS8427-DS CS8427-DZ CDB8427 RERR RMCK AES3 C & ...
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... Interrupt 1 Status (07h) (Read Only)............................................................................... 32 11.8 Interrupt 2 Status (08h) (Read Only)............................................................................... 33 11.9 Interrupt 1 Mask (09h)..................................................................................................... 33 11.10 Interrupt 1 Mode MSB (0Ah) & Interrupt 1 Mode LSB (0Bh)......................................... 33 11.11 Interrupt 2 Mask (0Ch) .................................................................................................. 34 11.12 Interrupt 2 Mode MSB (0Dh) & Interrupt 2 Mode LSB (0Eh) ........................................ 34 11.13 Receiver Channel Status (0Fh) (Read Only) ................................................................ 34 2 CS8427 DS477F3 ...
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... User Data Buffer Control (13h) ..................................................................................... 37 11.18 Q-Channel Subcode Bytes (14h - 1Dh) (Read Only) ......................................... 37 11.19 OMCK/RMCK Ratio (1Eh) (Read Only)........................................................................ 38 11.20 C-bit or U-bit Data Buffer (20h - 37h) ........................................................................... 38 11.21 CS8427 I.D. and Version Register (7Fh) (Read Only) ................................................. 38 12. PIN DESCRIPTION - SOFTWARE MODE ........................................................................... 39 13. HARDWARE MODE DESCRIPTION ................................................................................... 42 13.1 Serial Audio Port Formats ............................................................................................. 42 14 ...
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... Figure 3. SPI Mode timing............................................................................................................... 9 Figure 4. I²C Mode timing.............................................................................................................. 10 Figure 5. Recommended Connection Diagram for Software Mode............................................... 11 Figure 6. CS8427 Internal Block Diagram..................................................................................... 13 Figure 7. Software Mode Audio Data Flow Switching Options...................................................... 19 Figure 8. CS8427 Clock Routing................................................................................................... 20 Figure 9. AES3 Input to Serial Audio Output, Serial Audio Input to AES3 Out ............................. 21 Figure 11 ...
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... Notes: 2. Transient currents 100 mA will not cause SCR latch-up. DS477F3 Symbol Min VA+ (Note 1) VL+ 2.85 ‘-CS’, ‘CSZ’ & ‘-CZ’ ‘-DS’ & ‘-DZ’ Symbol VL+,VA+ (Note stg CS8427 Typ Max Units 4.5 5.0 5.5 V 3.3 or 5.0 5.5 V -10 - +70 °C -40 - +85 Min Max Units - 6.0 ...
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... VL+ = 3.3 V VL+ = 5.0 V VA+ VL+ = 3.3 V VL+ = 5.0 V Symbol Symbol ( VL+ = 5.0 V) (15 VL+ = 3 VL+ = 5.0 V) (15 VL (Note =0.4 V (Max). IL Symbol VL TXP VL+ = 3.3 V VL TXN VL+ = 3.3 V CS8427 Min Typ Max Units µ µ µ 44.8 ...
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... Notes: 6. Cycle-to-cycle locking to RXP/RXN using kHz external PLL filter components. 7. PLL is bypassed (RXD1:0 bits in the Clock Source Control register set to 10b), clock is input to the RMCK pin. DS477F3 = 20 pF. L Symbol (Note 6) (Note 7) (Note 7) CS8427 Min Typ Max Units µs 200 - - 4 ...
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... ILRCK OLRCK (input) t lrckd ISCLK OSCLK t (input SDIN SDOUT Figure 2. Audio Port Slave Mode and Data Input Timing CS8427 Min Typ Max Units - - ...
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... Figure 3. SPI Mode timing CS8427 Min Typ Max Units 0 - 6.0 MHz µs 1 ...
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... L Symbol f scl t buf t hdst t low t high t sust (Note 18) t hdd t sud susp Repeated Start t high sud t sust hdd Figure 4. I²C Mode timing CS8427 Min Typ Max Units - - 100 kHz µs 4 µs 4 µs 4 µs 4 µs 4 µ 250 - ...
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... CS8427 ILRCK OLRCK ISCLK OSCLK SDIN SDOUT RMCK SDA/CDOUT OMCK AD0/CS SCL/CCLK AD1/CDIN INT EMPH / RERR RST TCBL H/S AGND FILT DGND RFILT CFILT CRIP CS8427 +3 +5.0 V Digital Supply AES3/ Cable SPDIF Interface Equipment 3-wire Serial Audio Input Device Microcontroller 11 ...
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... In applications using AES3 in and AES3 out, the CS8427 can automatically transceive user data that conforms to the IEC60958 format. The CS8427 also gives the user access to the bits nec- essary to comply with the serial copy management system (SCMS). In applications where the user want to read/modi- ...
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... Digital Audio Transmission, by Clifton Sanchez excellent tutorial on SCMS available from the AES as preprint 3518. 4. DATA I/O FLOW AND CLOCKING OPTIONS The CS8427 can be configured for several connec- tivity alternatives, called data flows. ware Mode Audio Data Flow Switching Options” on www.aes.org or ...
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... By studying the following drawings and appropri- ately setting the Data Flow Control and Clock Source Control register bits, the CS8427 can be configured to fit a variety of customer require- ments. Please note that applications implementing both the Serial Audio Output Port and the AES3 ...
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... Conversely sub-frame where the MSB of the data is '0', all bits preceding the MSB in the sub-frame will also be '0'. The clocking of the input section of the CS8427 may be derived from the incoming ILRCK word rate clock, using the on-chip PLL. The PLL opera- tion is described in “ ...
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... Error Reporting and Hold Function While decoding the incoming AES3 data stream, the CS8427 can identify several kinds of error, in- provides dicated in the Receiver Error register. The UN- LOCK bit indicates whether the PLL is locked to “Ap- the incoming AES3 data. The V bit reflects the cur- rent validity bit status ...
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... AC3 or MPEG encoders, may not adhere to this convention, and the bit may not be properly set. The CS8427 AES3 receiver can detect such non-audio data. This is accomplished by looking for a 96-bit sync code, consisting of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872, and 0x4E1F ...
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... CS8427. The user can manually access the internal storage or configure the CS8427 to run in one of several automatic modes. The Appendix: Channel Status and User Data Buffer Management provides detailed descriptions of each automatic mode and describes methods of manually accessing the storage areas ...
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... The “mono mode” AES3 output stream may also be achieved by keeping the CS8427 in normal stereo mode and placing consecutive audio sam- ples in the left and right positions of an incoming data stream with a 48-kHz word rate ...
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... RXD1 multiplexer; RMCK is not bi-directional in this mode. 20 SIMS INC RMCKF MUX 1 0 CHANNEL STATUS ÷ PLL MEMORY USER BIT SWCLK MEMORY UNLOCK 0 MUX 1 RXD1 Figure 8. CS8427 Clock Routing CS8427 SERIAL SDOUT AUDIO OSCLK OUTPUT OLRCK TXN AES3 TRANSMIT TXP OUTC MUX 1 0 ÷ OMCK CLK[1:0] DS477F3 ...
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... I LRCK TXN I SCLK TXP SD IN Data Flow Control Bits TXD1-0: 0 SPD1- Figure 12. Input Serial Port to AES3 Transmitter NOTE: In this mode, ILRCK and ISCLK are inputs only. CS8427 Serial Audio Output PLL RMCK Clock Source Control Bits 10 OUTC INC: 0 RXD1-0: ...
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... Data [2] Y Data [3] AES3 Transmitter in Stereo Mode U[0] Data [5] Data [6] Data [7] Data [0]* Y Data [2]* Data [1]* Y Data [3]* AES3 Transmitter in Mono Mode CS8427 VCU[3] VCU[4] Data [8] X Data [4] Tsetup => 7.5% AES3 frame time Thold = 0 Tth > 3OMCK if TCBL is Input U[2] Data [8] X Data [4]* X Data [5]* Tsetup => ...
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... See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit Figure 15. Serial Audio Input Example Formats DS477F3 Channel A LSB MSB Channel A LSB MSB Channel A MSB LSB SISF* SIRES*[1:0] SIJUST* X 00 CS8427 Channel B LSB MSB Channel B LSB Channel B MSB SIDEL* SISPOL* SILRPOL MSB ...
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... U C MSB Frame 0 SOSF* SORES[1:0]* SOJUST Figure 16. Serial Audio Output Example Formats CS8427 Channel B LSB MSB Channel B LSB MSB Channel B MSB LSB Channel A Channel B LSB MSB MSB SODEL* SOSPOL* SOLRPOL* ...
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... CS8427 is being reset. The upper four bits of the seven bit address field are fixed at 0010b. To com- municate with a CS8427, the chip address field, which is the first byte sent to the CS8427, should be 0010b followed by the settings of the EMPH, AD1, and AD0. The eighth bit of the address is the R/W bit ...
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... Figure 17. Control Port Timing in SPI Mode Note 1 Note 2 ACK DATA7-0 ACK DATA7-0 ACK 0010 AD2-0 R/W AD1 and AD0 are determined by the state of the corresponding pins Figure 18. Control Port Timing in I²C Mode CS8427 R/W LSB MSB MSB LSB Note 3 Stop DS477F3 ...
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... INCR - Auto Increment Address Control Bit Default = ‘0’ Disable 1 - Enable MAP6:MAP0 - Register address Note: Reserved registers must not be written to during normal operation. Some reserved registers are used for test modes, which can completely alter the normal operation of the CS8427. DS477F3 ...
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... Do not change the received audio sample 11 - Reserved RMCKF - Select recovered master clock output pin frequency. Default = ‘0’ RMCK is equal to 256 * Fsi 1 - RMCK is equal to 128 * Fsi MUTEAES RMCKF MMR CS8427 INT1 INT0 TCBLD MMT MMTCS MMTLR DS477F3 ...
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... The transmitter clock (selecting using the OUTC bit in the Clock Source Control) must be present for the bypass mode to work. TXD1:TXD0 - AES3 Transmitter Data Source Default = ‘01’ Reserved 01 - Serial audio input port 10 - AES3 receiver 11 - Reserved DS477F3 TXD1 TXD0 CS8427 SPD1 SPD0 0 29 ...
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... RUN is set to 1. CLK1:0 - Output side master clock input (OMCK) frequency to output sample rate (Fso) ratio selector. If these bits are changed during normal operation, then always stop the CS8427 first (RUN = 0), write the new value, then start the CS8427 (RUN = 1). ...
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... Serial audio output port is in slave mode 1 - Serial audio output port is in master mode SOSF - OSCLK frequency (for master mode) Default = ‘0’ Fso 1 - 128 * Fso DS477F3 SIRES0 SIJUST SORES0 SOJUST CS8427 SIDEL SISPOL SILRPOL SODEL SOSPOL SOLRPOL 31 ...
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... Indicates the completion C-buffer transfer. See “Channel Status and User Data Buffer Man- agement” on page 51 for more information. RERR - A receiver error has occurred. The Receiver Error register may be read to determine the nature of the error which caused the interrupt CS8427 DETC EFTC RERR DS477F3 ...
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... Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These reg- isters default to 00 Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved DS477F3 DETU CS8427 EFTU QCH DETCM EFTCM RERRM DETC1 EFTC1 RERR1 DETC0 EFTC0 RERR0 33 ...
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... Received channel status block is in consumer format 1 - Received channel status block is in professional format DETUM DETU1 0 0 DETU0 AUX0 PRO CS8427 EFTUM QCHM EFTU1 QCH1 0 EFTU0 QCH0 AUDIO COPY ORIG DS477F3 ...
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... Confidence error. This is the logical OR of BIP and UNLOCK. BIP - Bi-phase error bit. Updated on sub-frame boundaries error 1 - Bi-phase error. This indicates an error in the received bi-phase coding. PAR - Parity bit. Updated on sub-frame boundaries error 1 - Parity error DS477F3 UNLOCK V CS8427 CONF BIP PAR 35 ...
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... Channel B information is displayed at EMPH pin and in the receiver channel status register. Channel B information is output during control port reads when CAM is set to 0 (One Byte Mode UNLOCKM CBMR DETCI CS8427 CONFM BIPM PARM EFTCI CAM CHS DS477F3 ...
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... UD - User data pin (U) direction specifier If this bit is changed during normal operation, then always stop the CS8427 first (RUN = 0), write the new value, then start the CS8427 (RUN = 1). Default = ‘0’ The U pin is an input. The U data is latched in on both rising and falling edges of OLRCK ...
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... Either channel status data buffer E or user data buffer E (provided UBM bits are set to block mode) is accessible using these register addresses. 11.21 CS8427 I.D. and Version Register (7Fh) (Read Only ID3 ID2 ID3 code for the CS8427. Permanently set to 0111 VER3:0 - CS8427 revision level. Revision A is coded as 0001 ORR4 ORR3 > ...
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... See “Appendix C: PLL Filter” on page 54 for recommended schematic and compo- nent values. 9 Reset (Input) - When RST is low, the CS8427 enters a low power mode and all internal RST states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase ...
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... Hardware/Software Mode Control (Input) - Determines the method of controlling the oper- H/S ation of the CS8427, and the method of accessing CS and U data. In software mode, device control and CS and U data access is primarily through the control port, using a microcontrol- ler. Hardware mode provides an alternate mode of operation and access to the CS and U data through dedicated pins ...
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... In SPI mode, CDIN is the input data line for the control port interface SCL/CCLK 28 Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and out of the CS8427. In I²C mode, SCL requires an external pull-up resistor to VL+ DS477F3 CS8427 ...
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... ILRCK Serial Serial Audio Audio Input Output C & U bit Data Buffer PRO/C COPY ORIG EMPH/U AUDIO/V TCBL Figure 19. Hardware Mode CS8427 Table 2 on page Table 3 on Table 4 on page 43, which define the Figure 15 on Figure 16 on page 24. SDIN APMS AES3 TXP ...
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... Table 2. Hardware Mode Start-up Options SOSF SORES1/0 SOJUST SISF SIRES1/0 SIJUST CS8427 Function SODEL SOSPOL SOLRPOL SIDEL SISPOL SILRPOL ...
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... See “Appendix C: PLL Filter” on page 54 for recommended schematic and component values. 9 Reset (Input) - When RST is low, the CS8427 enters a low power mode and all internal states RST are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase ...
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... Hardware/Software Mode Control (Input) - Determines the method of controlling the opera- H/S tion of the CS8427, and the method of accessing CS and U data. In software mode, device control and CS and U data access is primarily through the control port, using a microcontroller. Hardware mode provides an alternate mode of operation and access to the CS and U data through dedicated pins ...
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... APPLICATIONS 15.1 Reset, Power Down and Start-up When RST is low, the CS8427 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are mut- ed. When RST is high, the control port becomes operational and the desired settings should be loaded into the control registers ...
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... L 0.016 ∝ 0° DS477F3 D INCHES NOM MAX 0.098 0.104 0.008 0.012 0.017 0.020 0.011 0.013 0.705 0.713 17.70 0.295 0.299 0.050 0.060 0.407 0.419 10.00 0.026 0.050 4° 8° JEDEC #: MS-013 Controlling Dimension is Millimeters CS8427 MILLIMETERS MIN NOM MAX 2.35 2.50 2.65 0.10 0.20 0.30 0.33 0.42 0.51 0.23 0.28 0.32 17.90 18.10 7.40 7.50 7.60 1.02 1.27 1.52 10.34 10.65 0.40 ...
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... SEATING PLANE SIDE VIEW NOM MAX MIN -- 0.47 -- 0.006 0.05 0.035 0.04 0.80 0.012 0.19 0.386 BSC 9.60 BSC 0.256 6.30 0.177 4. 0.029 0.50 4° 8° 0° JEDEC #: MO-153 Controlling Dimension is Millimeters. CS8427 1 E1 END VIEW L NOTE MILLIMETERS NOM MAX -- 1.20 0.10 0.15 0.90 1.00 0.245 0.30 2,3 9.70 BSC 9.80 BSC 1 6.40 6.50 4.40 4.50 1 0.65 BSC -- 0.60 0.75 4° 8° DS477F3 ...
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... AES3 Transmitter External Components The output drivers on the CS8427 are designed to drive both the professional and consumer interfac- es. The AES3 specification for professional/broad- cast use calls for a 110 Ω source impedance and a balanced drive capability. Since the transmitter output impedance is very low, a 110 Ω ...
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... AES3 Receiver External Components The CS8427 AES3 receiver is designed to accept both the professional and consumer interfaces. The digital audio specifications for professional use call for a balanced receiver, using XLR con- nectors, with 110 Ω ±20% impedance. The XLR connector on the receiver should have female pins with a male shell. Since the receiver has a very high input impedance, a 110 Ω ...
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... AES3 Channel Status(C) Bit Management The CS8427 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384 bits), and also 384 bits of U information. The user may read from or write to these RAMs through the control port ...
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... E buffer actually gets transmitted and not overwrit- ten transfer. If the channel status block to transmit indicates PRO mode, then the CRCC byte is automatically calculated by the CS8427, and does not have to be written into the last byte of the block by the host mi- crocontroller. 18.1.2 Reserving the first 5 bytes in the E ...
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... In these situations, two byte mode should be used to access the E buffer. In this mode, a read will cause the CS8427 to out- put two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data ...
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... PLL first locks onto upon application of an AES3 data stream or after enabling the CS8427 clocks by set- ting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will return to its wide lock range mode and re-acquire a new nominal center sample rate ...
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... The VA+ and AGND traces extend back to their origin and are shown only in truncated form in the drawing. 1000 Crip pF Cfilt .1µF Figure 31. Recommended Layout Example CS8427 , a C0G or RIP , an FILT and the other three FILT 55 ...
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... Pre-October 2002 Revision SOIC & TSSOP (10-Digit 19.3.2 Locking to the RXP/RXN Receiver Inputs CS8427 parts that are configured to lock to only the RXP/RXN receiver inputs should use the exter- nal PLL component values listed in Table 6 and Revision R FILT A 0.909 A1 A2 Table 6 ...
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... Locking to the ILRCK Input CS8427 parts that are configured to lock to the IL- RCK input should use the external PLL component values listed in Table 8. Note that parts that need to lock to both ILRCK and RXP/RXN should use Fs Range Revision (kHz 32-96 A1/ ...
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... Jitter Attenuation Shown in Figure 33, Figure 34, Figure 35, and Fig- ure 36 are jitter attenuation plots for the various re- visions of the CS8427 when used with the appropriate external PLL component values ( −5 −10 −15 −20 − Jitter Frequency (Hz) Figure 33. Revision A ...
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... Figures 15 and 16 on page 23 and page 24. -Corrected AES3 Direct format in figure 16 on page 24 and text reference to AES3 Direct format on page 15. -Changed description of DETC, EFTC, DETU,and EFTU bits in “Control Port Register Bit Definitions” on page 32 and page 33. Table 9. Revision History CS8427 59 ...