M25PE40VMW6TG STMicroelectronics, M25PE40VMW6TG Datasheet
M25PE40VMW6TG
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M25PE40VMW6TG Summary of contents
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Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout Features SPI bus compatible serial interface 4 Mbit Page-Erasable Flash memory Page size: 256 bytes – Page Write (typical) – ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M25PE40 6.4 Read Status Register (RDSR ...
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List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M25PE40 List of figures Figure 1. Logic diagram - previous T7X process . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The Mbit (512Kb × 8 bit) Serial Paged Flash memory accessed by a high speed SPI- compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the ...
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M25PE40 Figure 1. Logic diagram - previous T7X process TSL Reset Table 1. Signal names Signal name (1) TSL or W Reset the previous T7X process the ...
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Signal description 2 Signal description 2.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 2.2 Serial Data Input (D) ...
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M25PE40 2.6 Write Protect (W) or Top Sector Lock (TSL) The Write Protect function is available in the T9HX process only (see note on page The Write Protect (W) input is used to freeze the size of the area of ...
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SPI modes 3 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the ...
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M25PE40 Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 5. SPI modes supported CPOL CPHA ...
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Operating features 4 Operating features 4.1 Sharing the overhead of modifying data To write or program one (or more) data bytes, two instructions are required: Write Enable (WREN), which is one byte, and a Page Write (PW) or Page Program ...
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M25PE40 4.3 A fast way to modify data The Page Program (PP) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously ...
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Operating features 4.7 Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by using specific instructions. See for a detailed description of the Status Register bits. 4.8 Protection ...
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M25PE40 4.8.2 Specific Hardware and Software protections The features a Hardware Protected mode, HPM, and two Software Protected modes, SPM1 and SPM2, that can be combined to protect the memory array as required. They are described below: HPM HPM in ...
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Operating features Table 2. Software protection truth table (Sectors 64-Kbyte granularity) Sector Lock Register Lock Write Down bit Lock bit The second Software Protected mode (SPM2) uses the Block ...
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M25PE40 5 Memory organization The memory is organized as: 2048 pages (256 bytes each) 524,288 bytes (8 bits each) 128 subsectors (32 Kbits, 4096 bytes each) 8 sectors (512 Kbits, 65536 bytes each) Each page can be individually: – programmed ...
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Memory organization Figure 6. Block diagram Reset TSL These features (in gray) are only available in the T7X process. 18/60 Control Logic I/O Shift Register Address Register and Counter 6FFFFh 00000h 256 bytes ...
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M25PE40 6 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is ...
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Instructions Table 5. Instruction set Instruction WREN Write Enable WRDI Write Disable RDID Read Identification (1) RDSR Read Status Register (1) WRLR Write to Lock Register (1) WRSR Write Status Register RDLR Read Lock Register READ Read Data Bytes FAST_READ ...
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M25PE40 6.1 Write Enable (WREN) The Write Enable (WREN) instruction The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page Program (PP), Page Erase (PE), and Sector Erase (SE) instruction. The Write Enable (WREN) ...
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Instructions 6.2 Write Disable (WRDI) The Write Disable (WRDI) instruction The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit ...
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... The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for STMicroelectronics. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (80h), and the memory capacity of the device in the second byte (13h) ...
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Instructions 6.4 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write cycle is in progress. When ...
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M25PE40 Figure 10. Read Status Register (RDSR) instruction sequence and Data-out sequence High Impedance Instruction Status Register Out 7 6 ...
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Instructions 6.5 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Note: The Status Register BPi and SRWD bits are available in the in the T9HX process only. See ...
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M25PE40 Table 8. Protection modes (T9HX process only, see W SRWD Signal Bit Protected 1 1 Hardware 0 1 Protected 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the ...
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Instructions 6.6 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the ...
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M25PE40 6.7 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23- ...
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Instructions 6.8 Read Lock Register (RDLR) Note: The Read Lock Register (RDLR) instruction is decoded only in the in the T9HX process (see Important note on page The device is first selected by driving Chip Select (S) Low. The instruction ...
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M25PE40 6.9 Page Write (PW) The Page Write (PW) instruction allows bytes to be written in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has ...
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Instructions Figure 15. Page Write (PW) instruction sequence MSB 1. Address bits A23 to A19 are Don’t Care 256 32/ ...
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M25PE40 6.10 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. ...
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Instructions Figure 16. Page Program (PP) instruction sequence MSB 1. Address bits A23 to A19 are Don’t Care 256 34/ ...
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M25PE40 6.11 Write to Lock Register (WRLR) Note: The Write to Lock Register (WRLR) instruction is decoded only in the in the T9HX process (see Important note on page The Write to Lock Register (WRLR) instruction allows bits to be ...
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Instructions 6.12 Page Erase (PE) The Page Erase (PE) instruction sets to 1 (FFh) all bits inside the chosen page. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) ...
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M25PE40 6.13 SubSector Erase (SSE) Note: The SubSector Erase (SSE) instruction is decoded only in the in the T9HX process (see Important note on page The SubSector Erase (SSE) instruction sets to 1 (FFh) all bits inside the chosen subsector. ...
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Instructions 6.14 Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) ...
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M25PE40 6.15 Bulk Erase (BE) Note: The Bulk Erase (BE) instruction is decoded only in the in the T9HX process (see note on page 6). The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be ...
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Instructions 6.16 Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while ...
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M25PE40 6.17 Release from Deep Power-down (RDP) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. ...
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Power-up and Power-down 7 Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay of ...
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M25PE40 Figure 24. Power-up timing (max) Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed V CC (min) Reset State of the Device V WI Table 11. Power-up timing and V ...
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Reset 8 Reset Driving Reset (Reset) Low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost. All the Lock bits are reset to 0 after a Reset Low ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 13. ...
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DC and AC parameters 11 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from ...
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M25PE40 Table 17. DC characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO Standby Current I CC1 (Standby and Reset modes) I Deep Power-down Current CC2 Operating Current I CC3 (FAST_READ) I Operating Current (PW) CC4 ...
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DC and AC parameters M Table 18. AC characteristics (25 MHz operation) Test conditions specified in Symbol Alt. Clock Frequency for the following instructions FAST_READ, PW, PP, PE, SE, DP, RDP WREN, WRDI, RDSR f Clock ...
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M25PE40 Table 19. AC characteristics (33 MHz operation) 33MHz only available for products marked since week 40 of 2005 Test conditions specified in Symbol Alt. Clock Frequency for the following f f instructions: FAST_READ, PW, PP, PE, SE ...
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DC and AC parameters Table 20. AC characteristics (50 MHz operation, Test conditions specified in Symbol Alt. Clock Frequency for the following instructions FAST_READ, RDLR, PW, PP, WRLR, PE, SE SSE, DP, RDP, WREN, WRDI, RDSR, ...
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M25PE40 Figure 26. Serial input timing S tCHSL C tDVCH D High Impedance Q Figure 27. Top Sector Lock (T7X process) or Write Protect (T9HX process) setup and hold timing TSL or W tTHSL tWHSL High Impedance ...
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DC and AC parameters Figure 28. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D 52/60 tCH tCLQV tQLQH tQHQL M25PE40 tCL tSHQZ LSB OUT AI01449e ...
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M25PE40 Table 21. Reset conditions Symbol Alt. ( RLRH RST t SHRH 1. Value guaranteed by characterization, not 100% tested in production. Table 22. Timings after a Reset Low pulse Symbol Alt. Parameter Reset t t Recovery RHSL ...
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Package mechanical 12 Package mechanical Figure 30. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead 6 × 5 mm, package outline 0. Drawing is not to ...
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M25PE40 Figure 31. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline A2 1. Drawing is not to scale. Table 24. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data Symbol ...
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Package mechanical Figure 32. SO8W – 8 lead Plastic Small Outline, 208 mils body width, package outline 1. Drawing is not to scale. Table 25. SO8W – 8 lead Plastic Small Outline, 208 mils body width, package mechanical data Symbol ...
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M25PE40 13 Part numbering Table 26. Ordering information scheme Example: Device Type M25PE = Page-Erasable Serial Flash memory Device Function Mbit (512Kb × 8) Operating Voltage 2 Package MW ...
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Revision history 14 Revision history Table 27. Document revision history Date 01-Apr-2004 09-Nov-2004 01-Dec-2004 11-Jan-2005 4-Oct-2005 11-Aug 2006 58/60 Revision 0.1 Document written Write Protect (W) pin replaced by Top Block Lock (TBL). Section 2.5: Reset (Reset) modified. Reset timings ...
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M25PE40 Table 27. Document revision history Date 15-Jan-2007 23-Jan-2007 Revision 50 MHz frequency added. SO8N package added, VFQFPN and SO8W package specifications updated (see mechanical). The sectors are further divided up into subsectors (see Memory organization). Bus master and memory ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...