MT47H64M8CF-37E Micron Semiconductor Products, MT47H64M8CF-37E Datasheet
MT47H64M8CF-37E
Related parts for MT47H64M8CF-37E
MT47H64M8CF-37E Summary of contents
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DDR2 SDRAM MT47H128M4 – 32 Meg Banks MT47H64M8 – 16 Meg Banks MT47H32M16 – 8 Meg Banks Features • RoHS compliant • +1.8V ±0.1V ...
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Table 1: Key Timing Parameters Speed Grade -25E 400 -25 400 -3E 400 -3 400 -37E 400 -5E 400 Table 2: Addressing Parameter Configuration Refresh count Row address Bank address Column address Figure 1: 512Mb DDR2 Part ...
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Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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MRS Command to ODT Update Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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State Diagram Figure 2: Simplified State Diagram OCD default Setting (E)MRS MRS EMRS Automatic Sequence Command Sequence Active power- down WRITE Writing WRITE AP Writing with auto precharge Notes: 1. This diagram provides the basic command flow not ...
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Functional Description The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an inter- face designed to transfer two data words per clock cycle at the ...
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Automotive Temperature The automotive temperature (AT) option, if offered, has two simultaneous require- ments: ambient temperature surrounding the device cannot be less than –40°C or greater than +105°C, and the case temperature cannot be less than –40°C or greater than ...
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Functional Block Diagrams The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory inter- nally configured as a multi-bank DRAM. Figure 3: 128 Meg x 4 Functional Block Diagram ODT Control CKE logic CK CK# CS# RAS# ...
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Figure 4: 64 Meg x 8 Functional Block Diagram ODT Control CKE logic CK CK# CS# RAS# CAS# WE# Refresh 14 Mode Row- counter registers address MUX Address A0–A13, 16 register BA0, BA1 2 control Column- 10 ...
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Ball Assignments and Descriptions Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View PDF: 09005aef82f1e6e2/Source: 09005aef821aed36 512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 ...
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Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View PDF: 09005aef82f1e6e2/Source: 09005aef821aed36 512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN ...
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Table 3: FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions x16 Ball x4, x8 Ball Number Number M8, M3, M7, – N2, N8, N3, N7, P2, P8, P3, M2, P7, R2 – H8, H3, H7, J2, J8, J3, ...
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Table 3: FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions (continued) x16 Ball x4, x8 Ball Number Number F3 K7, L7, F7, G7, RAS#, CAS G8, G2, H7, – H3, H1, H9, ...
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Table 3: FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions (continued) x16 Ball x4, x8 Ball Number Number A1, E1, M9, A1, E9, L1, H9 R1, J9 A9, C1, C3, A9, C1, C3, C7, C7, C9, G3, E9, ...
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Package Dimensions Figure 8: 60-Ball FBGA (12mm x 10mm) – x4, x8 SEATING PLANE C 0.12 C 60X Ø0.45 6.4 SOLDER BALL DIAMETER REFERS 0.8 TO POST-REFLOW TYP CONDITION. 8 12.0 ±0.15 Notes: 1. All dimensions are in ...
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Figure 9: 60-Ball FBGA (10mm x 10mm) – x4, x8 SEATING PLANE C 0.12 C 60X Ø0.45 0.80 TYP SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. 8.0 10.0 ±0.15 Notes: 1. All dimensions are in millimeters. PDF: 09005aef82f1e6e2/Source: 09005aef821aed36 ...
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Figure 10: 60-Ball FBGA (8mm x 10mm) – x4, x8 SEATING PLANE C 0.12 C 60X Ø0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. 8.0 Notes: 1. All dimensions are in millimeters. PDF: 09005aef82f1e6e2/Source: 09005aef821aed36 512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: ...
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Figure 11: 84-Ball FBGA (12mm x 12.5mm) – x16 SEATING PLANE C 0.12 C 84X Ø0.45 6.4 SOLDER BALL 0.8 DIAMETER REFERS TYP TO POST-REFLOW CONDITION. 11 12.0 ±0.15 Notes: 1. All dimensions are in millimeters. PDF: 09005aef82f1e6e2/Source: ...
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Figure 12: 84-Ball FBGA (10mm x 12.5mm) – x16 SEATING PLANE C 0.12 C 84X ∅0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. 11.2 Notes: 1. All dimensions are in millimeters. PDF: 09005aef82f1e6e2/Source: 09005aef821aed36 512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. ...
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Figure 13: 84-Ball FBGA (8mm x 12.5mm) – x16 SEATING PLANE A 0.12 A 84X ∅ 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. 11.2 Notes: 1. All dimensions are in millimeters. PDF: 09005aef82f1e6e2/Source: 09005aef821aed36 512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: ...
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FBGA Package Capacitance Table 4: Input Capacitance Parameter Input capacitance: CK, CK# Delta input capacitance: CK, CK# Input capacitance: Address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE, ODT Delta input capacitance: Address balls, bank address balls, CS#, RAS#, ...
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Electrical Specifications – Absolute Ratings Stresses greater than those listed in Table 5 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions oustide those ...
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Table 6: Temperature Limits Parameter Storage temperature Operating temperature: commercial Operating temperature: industrial Operating temperature: automotive Notes: 1. MAX storage case temperature; T Figure 14. This case temperature limit is allowed to be exceeded briefly during package reflow, as noted ...
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Table 7: Thermal Impedance Die Revision Package Substrate 60-ball 2-layer B 4-layer 84-ball 2-layer 4-layer D 60-ball 2-layer 4-layer 84-ball 2-layer 4-layer F 60-ball 2-layer 4-layer 84-ball 2-layer 4-layer 60-ball 2-layer Last shrink target 4-layer 84-ball 2-layer 4-layer Notes: 1. ...
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Electrical Specifications – Specifications and Conditions DD Table 8: General I Parameters DD I Parameters -187E RCD (I ) 13.125 58125 DD t 7.5 RRD (I ...
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Table 10: DDR2 I Specifications and Conditions DD Notes: 1–7 (page 27) apply to the entire table Parameter/Condition Operating one bank active-precharge current RAS = ...
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Table 10: DDR2 I Specifications and Conditions (continued) DD Notes: 1–7 (page 27) apply to the entire table Parameter/Condition Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus ...
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AC Timing Operating Specifications Table 11: AC Operating Specifications and Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet Not all speed grades listed may be supported for this device; refer to the title page ...
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Table 11: AC Operating Specifications and Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: ...
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Table 11: AC Operating Specifications and Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: ...
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Table 11: AC Operating Specifications and Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: ...
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Table 11: AC Operating Specifications and Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: ...
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Table 11: AC Operating Specifications and Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: ...
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Table 11: AC Operating Specifications and Conditions for -187E, -25E, -3E, -3, -37E, and -5E Speeds (Sheet Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: ...
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Notes 1. All voltages are referenced Tests for AC timing nominal reference/supply voltage levels, but the related specifications and the operation of the device are warranted for the full voltage range specified. ODT is dis- ...
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This parameter is not referenced to a specific voltage level but is specified when the device output is no longer driving ( 18. The inputs to the DRAM must be aligned to the associated clock, that is, the actual ...
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If the differential DQS slew rate is not equal to 2 V/ns, then the baseline val- ues must be derated by adding the values from Tables 30 and 31 on pages 55–56. If the ...
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DELAY is calculated from prior to CK, CK# being removed in a system RESET condition (see "RESET" on page 115). t 43. ISXR is equal to Figure 71 on page 106. t 44. CKE (MIN) of three clocks ...
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ODT DC Electrical Characteristics Table 13: ODT DC Electrical Characteristics All voltages are referenced to V Parameter R effective impedance value for 75 TT EMR (A6, A2 effective impedance value for 150 TT EMR (A6, A2) ...
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Figure 15: Single-Ended Input Signal Levels 1,150mV 1,025mV 936mV 918mV 900mV 882mV 864mV 775mV 650mV Notes: 1. Numbers in diagram reflect nominal DDR2-400/DDR2-533 values. PDF: 09005aef82f1e6e2/Source: 09005aef821aed36 DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN 512Mb: ...
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Table 16: Differential Input Logic Levels All voltages referenced to V Parameter DC input signal voltage DC differential input voltage AC differential input voltage AC differential cross-point voltage Input midpoint voltage Notes CK#, DQS, DQS#, LDQS, LDQS#, ...
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Output Electrical Characteristics and Operating Conditions Table 17: Differential AC Output Parameters Parameter AC differential cross-point voltage AC differential voltage swing Notes: 1. The typical value of V and V differential output signals must cross. Figure 17: Differential Output Signal ...
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Table 19: Output Characteristics Parameter Output impedance Pull-up and pull-down mismatch Output slew rate 1. Absolute specifications: 0°C ≤ T Notes: 2. Impedance measurement conditions for output source DC current OUT V DD rent: V between 0V and ...
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Output Driver Characteristics Figure 19: Full Strength Pull-Down Characteristics 120 100 Table 20: Full Strength Pull-Down Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 ...
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Figure 20: Full Strength Pull-Up Characteristics Table 21: Full Strength Pull-Up Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 PDF: 09005aef82f1e6e2/Source: 09005aef821aed36 DDR2_x4x8x16_Core2.fm - ...
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Figure 21: Reduced Strength Pull-Down Characteristics Table 22: Reduced Strength Pull-Down Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 PDF: 09005aef82f1e6e2/Source: 09005aef821aed36 DDR2_x4x8x16_Core2.fm - ...
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Figure 22: Reduced Strength Pull-Up Characteristics –10 –20 –30 –40 –50 –60 –70 Table 23: Reduced Strength Pull-Up Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 ...
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Power and Ground Clamp Characteristics Power and ground clamps are provided on the following input-only balls: Address balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT, and CKE. Table 24: Input Clamp Characteristics Voltage Across Clamp (V) 0.0 0.1 0.2 ...
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AC Overshoot/Undershoot Specification Some revisions will support the 0.9V maximum average amplitude instead of the 0.5V maximum average amplitude shown in Tables 25 and 26. Table 25: Address and Control Balls Applies to address balls, bank address balls, CS#, RAS#, ...
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Table 27: AC Input Test Conditions Parameter Input setup timing measurement reference level address balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT, DM, UDM, LDM, and CKE Input hold timing measurement reference level address balls, bank address balls, CS#, ...
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Input Slew Rate Derating For all input signals, the total by adding the data sheet value, respectively. Example: t IS, the nominal slew rate for a rising signal, is defined as the slew rate between the last crossing of V ...
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Table 28: DDR2-400/533 Setup and Hold Time Derating Values ( Command/ 2.0 V/ns Address Slew Δ t Rate (V/ns) IS 4.0 +187 3.5 +179 3.0 +167 2.5 +150 2.0 +125 1.5 +83 1.0 0 0.9 –11 0.8 –25 0.7 –43 ...
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Figure 26: Nominal Slew Rate for CK MIN MIN REF MAX MAX IL AC Setup slew rate falling signal Figure ...
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Figure 28: Nominal Slew Rate for CK MIN MIN REF MAX MAX IL AC Figure 29: Tangent Line for ...
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Table 30: DDR2-400/DDR2-533 All units are shown in picoseconds DQ 4.0 V/ns 3.0 V/ns Slew Δ Δ Δ Δ Rate (V/ns 2.0 125 45 125 45 1 1.0 ...
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Table 31: DDR2-667/DDR2-800/DDR2-1066 All units are shown in picoseconds DQ 2.8 V/ns 2.4 V/ns Slew Δ Δ Δ Δ Rate (V/ns 2.0 100 63 100 63 1 1.0 ...
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Table 32: Single-Ended DQS Slew Rate Derating Values Using Reference points indicated in bold; Derating values are to be used with base 2.0 V/ns 1.8 V/ (V/ns 2.0 130 53 ...
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Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS Reference points indicated in bold 2.0 V/ns 1.8 V/ (V/ns 2.0 355 341 355 341 1.5 364 340 364 ...
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Figure 30: Nominal Slew Rate for DQS 1 DQS MIN MIN REF MAX MAX ...
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Figure 32: Nominal Slew Rate for DQS 1 DQS MIN MIN REF MAX MAX IL AC Notes: ...
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Figure 34: AC Input Test Signal Waveform Command/Address Balls Logic levels V levels REF Figure 35: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) Logic levels V levels REF PDF: 09005aef82f1e6e2/Source: 09005aef821aed36 DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. ...
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Figure 36: AC Input Test Signal Waveform for Data with DQS (Single-Ended) Logic levels V levels REF Figure 37: AC Input Test Signal Waveform (Differential PDF: 09005aef82f1e6e2/Source: 09005aef821aed36 DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: ...
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Commands Truth Tables The following tables provide a quick reference of available DDR2 SDRAM commands, including CKE power-down modes and bank-to-bank commands. Table 36: Truth Table – DDR2 Commands Notes: 1–3 apply to the entire table CKE Previous Function Cycle ...
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Table 37: Truth Table – Current State Bank n – Command to Bank n Notes: 1–6 apply to the entire table Current State CS# RAS Any L H Idle Row ...
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The following states must not be interrupted by any executable command (DESELECT or NOP commands must be applied on each positive clock edge during these states): Refresh: Accessing mode register: Precharge all: 6. All states and sequences not shown ...
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Table 38: Truth Table – Current State Bank n – Command to Bank m Notes: 1–6 apply to the entire table Current State CS# RAS# Any Idle L L Row active, active, or precharge ...
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READ with auto precharge enabled/ WRITE with auto precharge enabled: The minimum delay from a READ or WRITE command with auto precharge enabled to a command to a different bank is summarized in Table 39: Table 39: Minimum Delay with ...
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LOAD MODE (LM) The mode registers are loaded via bank address and address inputs. The bank address balls determine which mode register will be programmed. See “Mode Register (MR)” on page 73. The LM command can only be issued when ...
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After a bank has been precharged the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if ...
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Operations Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Figure 38 illus- trates and the notes outline the sequence of progression required for power-up ...
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VTD REF Tb0 T0 Ta0 SSTL_18 LVCMOS 2 low level 2 CKE low level ODT Command NOP 3 ...
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A. Single power source: The V B. Multiple power sources CKE requires LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device power-up prior to V levels. Once CKE transitions to a high level, ...
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The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after the DLL RESET at Tf0. 15. DM represents DM for the x4, x8 configurations and UDM, LDM for the x16 configuration; DQS represents DQS, ...
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Figure 39: Mode Register (MR) Definition 1 BA2 BA1 M15 Notes: 1. M16 (BA2) is only applicable for densities >1Gb, reserved for future use, and must be pro- grammed to “0.” 2. ...
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Table 40: Burst Definition Starting Column Address Burst Length (A2, A1, A0 ...
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Power-Down Mode Active power-down (PD) mode is defined by bit M12, as shown in Figure 39 on page 74. PD mode allows the user to determine the active power-down mode, which determines performance versus power savings. PD mode bit M12 ...
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Figure 40: CAS Latency (CL CK# CK READ NOP Command DQS, DQS CK# CK READ NOP Command DQS, DQS# DQ Notes Posted CAS# additive latency (AL Shown ...
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Figure 41: Extended Mode Register Definition 1 BA2 BA1 E15 E14 Notes: 1. E16 (BA2) is only applicable for densities >1Gb, reserved for future use, and must be pro- grammed to “0.” 2. ...
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Anytime the DLL is disabled and the device is operated below 25MHz, any AUTORE- FRESH command should be followed by a PRECHARGE ALL command. Output Drive Strength The output drive strength is defined by bit E1, as shown in Figure ...
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ODT must be turned off prior to entering self refresh mode. During power-up and initial- ization of the DDR2 SDRAM, ODT should be disabled until the EMR command is issued. This will enable the ODT feature, at which point the ...
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Figure 43: WRITE Latency T0 T1 CK# CK Command ACTIVE n WRITE n t RCD (MIN) DQS, DQS# DQ Notes Extended Mode ...
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Extended Mode Register 3 (EMR 3) The extended mode register 3 (EMR3) controls functions beyond those controlled by the mode register. Currently all bits in EMR3 are reserved, as shown in Figure 45 on page 82. The EMR3 is programmed ...
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Figure 46: Example: Meeting T0 T1 CK# CK Command ACT NOP Row Address Bank x Bank address t RRD A subsequent ACTIVATE command to a different row in the same bank can only be issued after the previous active row ...
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READ READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row ...
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Figure 48: READ Latency CK# CK Command READ Bank a, Address DQS, DQS# DQ CK# CK Command READ Bank a, Address DQS, DQS# DQ CK# CK Command READ Bank a, Address DQS, DQS# DQ Notes data-out ...
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Figure 49: Consecutive READ Bursts CK# CK Command Address DQS, DQS# DQ CK# CK Command Address DQS, DQS# DQ Notes ( data-out from column n (or column b Three subsequent ...
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Figure 50: Nonconsecutive READ Bursts CK# CK Command Address DQS, DQS# DQ CK# CK Command Address DQS, DQS# DQ Notes ( data-out from column n (or column b Three subsequent ...
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Figure 52: READ-to-WRITE CK# CK Command ACT n NOP READ n DQS, DQS# t RCD = Notes Shown with nominal READ ...
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Figure 54: READ-to-PRECHARGE – CK# CK Command Address A10 DQS, DQS# DQ Notes ( 3 RTP ≥ 2 clocks Shown with nominal READ ...
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Table 41: READ Using Concurrent Auto Precharge From Command (Bank n) READ with READ or READ with auto precharge auto WRITE or WRITE with auto precharge precharge PRECHARGE or ACTIVATE Figure 55: Bank Read – Without Auto Precharge T0 T1 ...
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Figure 56: Bank Read – with Auto Precharge CKE Command 1 NOP 1 ACT Address RA A10 RA Bank address Bank x DM Case (MIN) and t DQSCK (MIN) DQS, DQS# ...
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Figure 57: x4, x8 Data Output Timing – T1 CK# CK DQS, DQS (last data valid (first data no longer valid) DQ (last data valid) ...
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Figure 58: x16 Data Output Timing – CK# CK LDQS, LDSQ (last data valid (first data no longer valid (last data valid) ...
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Figure 59: Data Output Timing – CK# CK DQS, DQS# or LDQS, LDQS#/UDQ, UDQS (last data valid) DQ (first data valid) All DQs collectively 4 Notes: 1. READ command with ...
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Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide continuous flow of input data. The first data element from the new burst is applied after the last element of a completed burst. The new ...
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Figure 60: WRITE Burst Command Address t DQSS (NOM) DQS, DQS# t DQSS (MIN) DQS, DQS# t DQSS (MAX) DQS, DQS# Notes: 1. Subsequent rising DQS signals must align to the clock within data-in for column ...
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Figure 61: Consecutive WRITE-to-WRITE Command Address t DQSS (NOM) DQS, DQS# Notes: 1. Subsequent rising DQS signals must align to the clock within etc. = data-in for column b, etc. 3. Three subsequent elements of data-in are ...
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Figure 63: WRITE Interrupted by WRITE T0 T1 CK# CK WRITE 1 a NOP 2 WRITE 3 b Command Valid 5 Address A10 DQS, DQS 2-clock requirement Notes required and auto precharge ...
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Figure 64: WRITE-to-READ T0 T1 CK# CK Command WRITE NOP Bank a, Address Col b t DQSS (NOM) WL ± t DQSS DQS, DQS DQSS t DQSS (MIN) DQS, DQS DQSS ...
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Figure 65: WRITE-to-PRECHARGE T0 T1 CK# CK Command WRITE NOP Bank a, Address Col b t DQSS (NOM DQSS DQS#, DQS DQSS (MIN DQSS DQS#, DQS DQSS (MAX) ...
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Figure 66: Bank Write – Without Auto Precharge CKE NOP 1 Command ACT RA Address A10 RA Bank address Bank x DQS, DQS Notes: 1. NOP commands are shown for ease ...
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Figure 67: Bank Write – with Auto Precharge CKE NOP 1 Command ACT RA Address A10 RA Bank address Bank x DQS, DQS Notes: 1. NOP commands are shown for ease ...
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Figure 68: WRITE – DM Operation CK CKE NOP 1 NOP 1 Command ACT Address RA A10 RA Bank address Bank x DQS, DQS Notes: 1. NOP commands are ...
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Figure 69: Data Input Timing CK# DQS, DQS# t Notes: 1. DSH (MIN) generally occurs during t 2. DSS (MIN) generally occurs during 3. Subsequent rising DQS signals must align to the clock within 4. WRITE command issued at T0. ...
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REFRESH The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average interval of 7.8125µs (MAX) and all rows in all banks must be refreshed at least once every 64ms. The refresh period begins when the REFRESH command is registered ...
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SELF REFRESH The SELF REFRESH command is initiated with CKE is LOW. The differential clock should remain stable and meet mode. The procedure for exiting self refresh requires a sequence of commands. First, the differential clock must be stable and ...
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Power-Down Mode DDR2 SDRAMs support multiple power-down modes that allow significant power savings over normal operating modes. CKE is used to enter and exit different power- down modes. Power-down entry and exit timings are shown in Figure 72 on page ...
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Figure 72: Power-Down Valid 1 Command NOP CKE Address Valid DQS, DQS Enter power-down mode 6 Notes this command is a PRECHARGE (or if the device is already ...
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Table 43: Truth Table – CKE Notes 1–4 apply to the entire table CKE Previous Cycle Current State ( Power-down L L Self refresh L L Bank(s) active H All banks idle Notes: 1. CKE ...
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Figure 73: READ-to-Power-Down or Self Refresh Entry T0 T1 CK# CK Command READ NOP CKE Address Valid A10 DQS, DQS Notes the example shown, READ burst completes at T5; earliest power-down or self refresh ...
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Figure 75: WRITE-to-Power-Down or Self-Refresh Entry T0 T1 CK# CK Command WRITE NOP CKE Address Valid A10 DQS, DQS Notes: 1. Power-down or self refresh entry may occur after the WRITE burst completes. Figure 76: WRITE ...
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Figure 77: REFRESH Command-to-Power-Down Entry CK# CK Command CKE Notes: 1. The earliest precharge power-down entry may occur is at T2, which is 1 × REFRESH command. Precharge power-down entry occurs prior to Figure 78: ACTIVATE Command-to-Power-Down Entry CK# Command ...
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Figure 79: PRECHARGE Command-to-Power-Down Entry CK# Command Address A10 CKE Notes: 1. The earliest precharge power-down entry may occur is at T2, which is 1 × CHARGE command. Precharge power-down entry occurs prior to Figure 80: LOAD MODE Command-to-Power-Down Entry ...
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DLL must be reset via MR after precharge power-down exit. Depending on the new clock frequency, additional LM commands might be required to adjust ...
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RESET CKE LOW Anytime DDR2 SDRAM applications may go into a reset state anytime during normal operation application enters a reset condition, CKE is used to ensure the DDR2 SDRAM device resumes normal operation after reinitializing. All data ...
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Figure 82: RESET Function T0 T1 CK# CK CKE ODT NOP 2 Command READ DM 3 Address Col n A10 Bank address Bank a High-Z DQS 3 High Notes Either NOP or ...
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ODT Timing Once a 12ns delay ( enabled via the EMR LOAD MODE command, ODT can be accessed under two timing categories. ODT will operate either in synchronous mode or asynchronous mode, depending on the state of CKE. ODT can ...
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Figure 83: ODT Timing for Entering and Exiting Power-Down Mode Synchronous t ANPD (3 First CKE latched LOW CKE Any mode except self refresh mode Applicable modes t t AOND/ AOFD Applicable timing parameters MRS Command to ODT Update Delay ...
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Figure 85: ODT Timing for Active or Fast-Exit Power-Down Mode CK# Command Address CKE ODT R Figure 86: ODT Timing for Slow-Exit or Precharge Power-Down Modes CK# CK Command Address CKE ODT R PDF: 09005aef82f1e6e2/Source: 09005aef821aed36 DDR2_x4x8x16_Core2.fm - 512Mb DDR2: ...
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Figure 87: ODT Turn-Off Timings When Entering Power-Down Mode CK# CK Command CKE ODT R ODT R Figure 88: ODT Turn-On Timing When Entering Power-Down Mode CK# CK Command CKE ODT R ODT R PDF: 09005aef82f1e6e2/Source: 09005aef821aed36 DDR2_x4x8x16_Core2.fm - 512Mb ...
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Figure 89: ODT Turn-Off Timing When Exiting Power-Down Mode T0 T1 CK# CK Command NOP NOP NOP CKE t CKE (MIN) ODT R TT ODT R TT PDF: 09005aef82f1e6e2/Source: 09005aef821aed36 DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C ...
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Figure 90: ODT Turn-On Timing When Exiting Power-Down Mode T0 T1 CK# CK Command NOP NOP CKE t CKE (MIN) ODT R TT ODT R TT 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com ...