MT48LC16M8A2 Micron Semiconductor Products, MT48LC16M8A2 Datasheet
MT48LC16M8A2
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MT48LC16M8A2 Summary of contents
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... SDRAM MT48LC32M4A2 – 8 Meg banks MT48LC16M8A2 – 4 Meg banks MT48LC8M16A2 – 2 Meg banks For the latest data sheet, refer to Micron’s Web site: Features • PC100- and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • ...
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... Table 3: 128Mb SDRAM Part Numbers Part Number MT48LC32M4A2TG MT48LC32M4A2P MT48LC16M8A2TG MT48LC16M8A2P MT48LC16M8A2FB MT48LC16M8A2BB MT48LC8M16A2TG MT48LC8M16A2P MT48LC8M16A2B4 MT48LC8M16A2F4 Notes: 1. FBGA Device Decode: http://www.micron.com/support/FBGA/FBGA.asp General Description The Micron containing 134,217,728 bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’ ...
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Table of Contents Features 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures 54-Pin TSOP Pin Assignment (Top View) 1 Figure 2: 60-Ball FBGA Ball Assignments (Top View), 16 Meg x 8, 8mm x 16mm . . . . . . . . . . . . . . . ...
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Figure 57: 60-Ball FBGA “FB/BB” Package (x8 device), 8mm x 16mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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FBGA Ball Assignments Figure 2: 60-Ball FBGA Ball Assignments (Top View), 16 Meg x 8, 8mm x 16mm PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. M ...
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Figure 3: 54-Ball VFBGA Assignments (Top View), 8 Meg x 16, 8mm x 8mm Notes: 1. The balls at A4, A5, and A6 are not in the physical package. They are ...
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Functional Block Diagrams Figure 4: 32 Meg x 4 SDRAM CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER 11 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. M 10/07 EN ...
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Figure 5: 16 Meg x 8 SDRAM CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER 10 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. M 10/ BANK0 ROW- ...
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Figure 6: 8 Meg x 16 SDRAM CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTER COUNTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER 9 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. M 10/ BANK0 ROW- ...
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Pin/Ball Descriptions Table 4: Pin/Ball Descriptions 54-Ball 60-Ball 54-Pin TSOP VFBGA FBGA 16, 17, 18 F9, F7, F8 J7, J8 – 15, 39 E8, F1 20, 21 G7, G8 M8, M7 23–26, ...
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Table 4: Pin/Ball Descriptions (continued) 54-Ball 60-Ball 54-Pin TSOP VFBGA FBGA A8, B9, B8, 10, 11, 13, C9, C8, D9, 42, 44, 45, D8, E9, E1, 47, 48, 50, D2, D1, C2, 51, 53 C1, ...
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Functional Description In general, the 128Mb SDRAMs (8 Meg banks, 4 Meg banks, and 2 Meg banks) are quad-bank DRAMs that operate at 3.3V and include a synchronous ...
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Wait at least given. All banks will complete their precharge, thereby placing the device in the all banks idle state. 8. Issue an AUTO REFRESH command. 9. Wait at least are allowed. 10. Issue an AUTO REFRESH command. 11. ...
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When a READ or WRITE command is issued, a block of columns equal to the BL is effec- tively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if ...
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Figure 7: Mode Register Definition A11, A10 = “0, 0” to ensure compatibility with future devices. Write Burst Mode A9 0 Programmed Burst Length 1 Single Location Access A8 A7 A6–A0 Operating Mode 0 0 Defined Standard Operation – – ...
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Table 5: Burst Definition Burst Length Full page (y) Notes: 1. For full-page accesses 2,048 (x4 1,024 (x8), and y = 512 (x16). 2. For A1–A9, A11 (x4), A1–A9 (x8), ...
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Table 6: CAS Latency Figure 8: CAS Latency COMMAND COMMAND Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combi- nations of values for M7 and M8 are reserved for future use ...
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Commands Table 7 provides a quick reference of available commands. This is followed by a written description of each command. Three additional truth tables appear following “Opera- tion” on page 23; these tables provide current state/next state information. Table 7: ...
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LOAD MODE REGISTER (LMR) The mode register is loaded via inputs A0–A11 (A12 should be driven LOW). See “Mode Register” heading in the “Register Definition” section on page 15. The LMR command can only be issued when all banks are ...
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A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is ...
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The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. After CKE ...
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Figure 9: Activating a Specific Row in a Specific Bank A0–A10, A11 BA0, BA1 Figure 10: Example: Meeting CLK COMMAND Reads READ bursts are initiated with a READ command, as shown in Figure 11 on page 25. The starting column ...
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Figure 11: READ Command A0–A9, A11: x4 A0–A9: x8 A0–A8: x16 A9, A11: x16 Figure 12: CAS Latency COMMAND COMMAND PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. M 10/07 EN CLK CKE HIGH CS# RAS# CAS# WE# COLUMN ADDRESS A11: x8 ...
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Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be ...
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Figure 14: Random READ Accesses COMMAND ADDRESS COMMAND ADDRESS Notes: 1. Each READ command may be to any bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length ...
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The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 15 shows the case where the clock frequency allows for bus ...
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This is shown in Figure 17 for each possible CL; data element either the last of a burst of four or the last desired of ...
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Figure 18: Terminating a READ Burst COMMAND ADDRESS COMMAND ADDRESS Notes: 1. DQM is LOW. WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 19 on page 31. The starting column and bank addresses are provided ...
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Figure 19: WRITE Command A0–A9, A11: x4 A0–A9: x8 A0–A8: x16 A9, A11: x16 Figure 20: WRITE Burst COMMAND ADDRESS Notes DQM is LOW. Data for any WRITE burst may be truncated with a subsequent WRITE ...
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A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 22 on page 32, ...
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Figure 23: WRITE-to-READ COMMAND ADDRESS Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not acti- vated), and a full-page WRITE burst may be ...
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Figure 24: WRITE-to-PRECHARGE CLK ≥ 15ns DQM COMMAND ADDRESS CLK < 15ns DQM COMMAND ADDRESS Notes: 1. DQM could remain LOW in this example if the WRITE burst is a fixed length ...
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PRECHARGE The PRECHARGE command (see Figure 26) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subse- quent row access some specified time ( ...
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Figure 27: Power-Down CLK CKE COMMAND All banks idle Enter power-down mode Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered low. In the clock suspend mode, the internal clock is ...
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Figure 29: Clock Suspend During READ Burst INTERNAL CLOCK COMMAND ADDRESS Notes: 1. For this example greater, and DQM is LOW. BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming ...
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Figure 30: READ With Auto Precharge Interrupted by a READ CLK COMMAND BANK n Internal States BANK m ADDRESS DQ Notes: 1. DQM is LOW. Figure 31: READ With Auto Precharge Interrupted by a WRITE CLK READ - AP COMMAND ...
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Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after valid data WRITE to bank n will be ...
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Table 8: Truth Table 2 – CKE Notes: 1–4 CKE CKE Current State Power-down Self refresh Clock suspend L H Power-down Self refresh Clock suspend H L All banks idle All banks idle Reading ...
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Table 9: Truth Table 3 – Current State Bank n, Command to Bank n Notes: 1–6; notes appear below and on next page Current State CS# RAS# Any Idle ...
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The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Accessing mode register: Precharging all: 6. All states and sequences not ...
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Table 10: Truth Table 4 – Current State Bank n, Command to Bank m Notes: 1–6; notes appear below and on next page Current State CS# RAS# Any Idle X X Row L L activating, L ...
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A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m ...
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Electrical Specifications Stresses greater than those listed in Table 11 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...
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Table 12: Temperature Limits Parameter Operating case temperature: Commercial Industrial Junction temperature: Commercial Industrial Ambient temperature: Commercial Industrial Peak reflow temperature Notes: 1. MAX operating case temperature, T side of the device, as shown in Figure 34, Figure 35, and ...
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Figure 34: Example Temperature Test Point Location, 54-Pin TSOP: Top View Test point Figure 35: Example Temperature Test Point Location, 54-Ball VFBGA: Top View Test point Figure 36: Example Temperature Test Point Location, 60-Ball FBGA: Top View Test point PDF: ...
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Table 14: DC Electrical Characteristics and Operating Conditions Notes notes appear on page 51; V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Input leakage current: Any input ...
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Table 16: Capacitance Note: 2; notes appear on page 51 Parameter – TSOP “TG” Package Input capacitance: CLK Input capacitance: All other input-only pins Input/output capacitance: DQ Parameter – FBGA “FB” Input capacitance: CLK Input capacitance: All other input-only pins ...
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Table 18: AC Functional Characteristics Notes 11; notes appear on page 51 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode ...
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Notes 1. All voltages referenced This parameter is sampled. V biased at 1.4V with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used ...
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V IH cannot be greater than one-third of the cycle rate pulse width 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during ...
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Timing Diagrams Figure 37: Initialize and Load Mode Register CLK ( ( ) ) t CKH t CKS ( ( ) ) CKE ( ( ) ) t CMS t CMH t CMS t CMH ( ...
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Figure 38: Power-Down Mode CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM / DQML, DQMH A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two ...
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Figure 39: Clock Suspend Mode CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM / DQML, DQMH ...
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Figure 40: Auto Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM / DQML, DQMH A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ ...
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Figure 41: Self Refresh Mode T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE NOP A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High ...
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Figure 42: READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ROW ...
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Figure 43: READ – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ENABLE ...
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Figure 44: Single READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ...
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Figure 45: Single READ – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMU A0–A9, A11 ROW ...
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Figure 46: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ENABLE AUTO ...
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Figure 47: READ – Full-Page Burst CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 ...
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Figure 48: READ – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ENABLE AUTO ...
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Figure 49: WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH A0–A9, A11 COLUMN m ...
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Figure 50: WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 A0–A9, ...
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Figure 51: Single WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMU A0–A9, A11 ROW ...
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Figure 52: Single WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH NOP 3 COMMAND ACTIVE DQM / DQML, DQMH A0–A9, A11 ROW t ...
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Figure 53: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM / DQML, DQMH COLUMN m 2 A0–A9, A11 ...
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Figure 54: WRITE – Full-Page Burst CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM / DQML, DQMH A0–A9, A11 ROW ROW A10 ...
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Figure 55: WRITE – DQM Operation CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM / DQML, DQMH A0–A9, A11 ROW ROW A10 t AS ...
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Package Dimensions Figure 56: 54-Pin Plastic TSOP (400 mil) PIN # 0. 1.00 10.16 ±0.08 11.76 ±0.20 +0.03 0.15 -0.02 Notes: 1. All dimensions in millimeters. 2. Package width and length do not include mold ...
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Figure 57: 60-Ball FBGA “FB/BB” Package (x8 device), 8mm x 16mm 0.155 ±0.013 0.850 ±0.05 60X Ø 0.45 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. PRE- REFLOW DIAMETER IS 0. 0.33 NSMD BALL PAD. BALL A8 8.00 ±0.05 ...
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Figure 58: 54-Ball VFBGA “F4/B4” Package (x16 device), 8mm x 8mm 0.65 ±0.05 SEATING PLANE C 0.10 C 54X Ø0.45 ±0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS 0.42. BALL A9 6.40 3.20 3.20 ...