MT49H8M36BM-25 Micron Semiconductor Products, MT49H8M36BM-25 Datasheet
MT49H8M36BM-25
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MT49H8M36BM-25 Summary of contents
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CIO RLDRAM MT49H32M9 – 32 Meg Banks MT49H16M18 – 16 Meg Banks MT49H8M36 – 8 Meg Banks Features • 400 MHz DDR operation (800 Mb/s/pin data rate) • ...
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Figure 2: 288Mb RLDRAM II CIO Part Numbers Configuration 32 Meg Meg Meg x 36 Notes: 1. The FBGA package is being phased out. BGA Part Marking Decoder Due to space limitations, BGA-packaged components ...
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Table of Contents BGA Part Marking Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Lisf of Tables Table 1: 64 Meg x 9 Ball Assignments (Top View) 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . ...
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General Description The Micron designed for high bandwidth data storage—telecommunications, networking, and cache applications, etc. The chip’s 8-bank architecture is optimized for sustainable high speed operation. The DDR I/O interface transfers two data words per clock cycle at the I/O ...
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State Diagram Figure 3: Simplified State Diagram WRITE PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2.5V V Initialization sequence DSEL/NOP MRS Automatic sequence Command sequence HSTL, CIO, RLDRAM II ...
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Functional Block Diagrams Figure 4: 32 Meg x 9 Functional Block Diagram ZQ ODT control CK CK# Control CS# logic REF# WE# Refresh 13 counter Mode register Row- address MUX 18 13 A0–A20 1 Address BA0–BA2 24 register 3 8 ...
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Figure 5: 16 Meg x 18 Functional Block Diagram ZQ ODT control CK CK# Control CS# logic REF# WE# Refresh 13 counter Mode register Row- address MUX 18 13 A0–A19 1 Address 23 BA0–BA2 register Notes: ...
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Figure 6: 8 Meg x 36 Functional Block Diagram ZQ ODT control CK CK# Control CS# logic REF# WE# Refresh 13 counter Mode register Row- address MUX 18 13 A0–A18 1 Address 22 BA0–BA2 register Notes: ...
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Ball Assignments and Descriptions Table 1: 32 Meg x 9 Ball Assignments (Top View) 144-Ball µBGA REF SS EXT DNU DNU DNU DNU ...
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Table 2: 16 Meg x 18 Ball Assignments (Top View) 144-Ball µBGA REF SS EXT DNU DQ4 DNU DQ5 A22 DNU DQ6 ...
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Table 3: 8 Meg x 36 Ball Assignments (Top View) 144-Ball µBGA REF SS EXT B V DQ8 DQ9 DQ10 DQ11 TT D A22 DQ12 DQ13 2 E A21 DQ14 ...
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Table 4: Ball Descriptions Symbol Type A0–A20 Input Address inputs: A0–A20 define the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising ...
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Table 4: Ball Descriptions (continued) Symbol Type DNU – Do not use: These balls may be connected to ground. Note that if ODT is enabled, these pins will be connected – No function: These balls can be ...
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Package Dimensions Figure 7: 144-Ball µBGA 10.70 CTR SEATING PLANE 2.41 CTR A 0.08 A 144X Ø 0.45 DIMENSIONS APPLY 8.80 TO SOLDER BALLS POST REFLOW. THE BALL A12 PRE-REFLOW BALL MOLD DIAMETER IS 0. COMPOUND 0.40 SMD ...
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Figure 8: 144-Ball FBGA SEATING PLANE A 0.10 A 144X Ø 0.55 DIMENSIONS APPLY TO SOLDER BALLS POST MOLD REFLOW. THE PRE-REFLOW COMPOUND BALL IS Ø0. Ø0.40 NSMD BALL PAD. BALL A12 17.00 8.50 4.40 Notes: 1. All ...
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Electrical Specifications – I Table 5: I Operating Conditions and Maximum Limits DD Description t Standby current CK = idle; All banks idle; No inputs toggling Active standby CS commands; Bank address current incremented and half address/data ...
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Notes ≤ Input slew rate is specified in Table 8 on page 19. 4. Definitions for I 4a. LOW is defined as V 4b. HIGH is defined as V 4c. Stable ...
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Electrical Specifications – AC and DC Absolute Maximum Ratings Stresses greater than those listed in Table 6 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any ...
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On-die termination may be selected using mode register bit 9 (see Figure 11 on page 32). A resistance device, I 10. If MRS bit use RQ = ...
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Table 9: Differential Input Clock Operating Conditions Notes 1–4 apply to the entire table; Unless otherwise noted: +0°C ≤ T Parameter/Condition Clock input voltage level: CK and CK# Clock input differential voltage: CK and CK# Clock input differential voltage: CK ...
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Input Slew Rate Derating Table 10 on page 22 and Table 11 on page 23 define the address, command, and data setup and hold derating values. These values are added to the default t t AH/ CH/ the 2 V/ns ...
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Table 10: Address and Command Setup and Hold Derating Values Command Address Slew AS REF Rate (V/ns) CK/CK# Crossing 2.0 0 1.9 5 1.8 11 1.7 18 1.6 25 1.5 33 1.4 43 1.3 54 1.2 ...
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Table 11: Data Setup and Hold Derating Values t Data Slew Rate REF (V/ns) CK/CK# Crossing 2.0 0 1.9 5 1.8 11 1.7 18 1.6 25 1.5 33 1.4 43 1.3 54 1.2 67 1.1 82 1.0 ...
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Figure 10: Nominal AS/ CS/ Table 12: Capacitance Notes 1–2 apply to entire table Description Address/control input capacitance Input/output capacitance (DQ, DM, and QK/QK#) Clock capacitance (CK/CK#, and DK/DK#) JTAG pins Notes: 1. Capacitance is not tested on ...
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Table 13: AC Electrical Characteristics: -25, -33, -5 Notes 1–4 (page 39) apply to the entire table Description Symbol Clock Input clock cycle time Input data clock cycle time t Clock jitter: period JIT t Clock jitter: cycle-to-cycle t Clock ...
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Notes 1. All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK# and to the crossing point with V 2. Outputs measured with equivalent load: 3. Tests for AC timing nominal reference/supply voltage levels, but ...
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Temperature and Thermal Impedance It is imperative that the RLDRAM device’s temperature specifications, shown in Table 14, be maintained in order to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step ...
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Table 15: Thermal Impedance θ JA (°C/W) Package Substrate Airflow = 0m/s µBGA 2-layer 4-layer FBGA 2-layer 4-layer Notes: Thermal impedance data is based on a number of samples from multiple lots and should be viewed as a typical number. ...
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Commands The following table provides descriptions of the valid commands of the RLDRAM. All input states or sequences not shown are illegal or reserved. All command and address inputs must meet setup and hold times around the rising edge of ...
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MODE REGISTER SET (MRS) The mode register set stores the data for controlling the operating modes of the memory. It programs the RLDRAM configuration, burst length, test mode, and I/O options. During an MRS command, the address inputs A0–A17 are ...
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Figure 11: Mode Register Definition in Nonmultiplexed Address Mode M8 Internal 50Ω 6 (default Notes: 1. A10–A17 must be set to zero; A18–An = “Don’t Care.” not used in MRS not ...
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Configuration Tables Table 18 shows the different configurations that can be programmed into the mode register. The WRITE latency is equal to the READ latency plus one in each configuration in order to maximize data bus utilization. Bits M0, M1, ...
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Figure 12: Read Burst Lengths T0 T1 CK# CK COMMAND READ NOP Bank a, ADDRESS Col QK# QK QVLD DQ QK# QK QVLD DQ QK# QK QVLD DQ Notes data-out from bank ...
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The data bus efficiency in continuous burst mode is only affected when using the setting since the device requires two clocks to read and write the data. The bank addresses are delivered ...
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READ command is issued. Similarly, ODT is designed to switch on at the DQs after the RLDRAM has issued the last piece of data. The DM pin will always be terminated. See section entitled “Operations” on ...
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WRITE Write accesses are initiated with a WRITE command, as shown in Figure 14. The address needs to be provided during the WRITE command. During WRITE commands, data will be registered at both edges of DK according to the programmed ...
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READ Read accesses are initiated with a READ command, as shown in Figure 15. Addresses are provided with the READ command. During READ bursts, the memory device drives the read data edge-aligned with the QKx signals. After ...
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AUTO REFRESH (AREF) AREF is used to perform a REFRESH cycle on one row in a specific bank. Because the row addresses are generated by an internal refresh counter for each bank, the external address balls are “Don’t Care.” The ...
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Operations INITIALIZATION The RLDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operations or permanent damage to the device. The following sequence is used for power-up: 1. Apply ...
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Figure 17: Power-Up/Initialization Sequence V EXT REF CK CKH t CKL DKL t DKH COMMAND NOP NOP DM ADDRESS BANK ADDRESS ...
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Figure 18: Power-Up/Initialization Flow Chart Step Notes: 1. The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 ...
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WRITE Figure 19: WRITE Burst T0 T1 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Add n t CKDK (NOM DK CKDK (MIN DK CKDK (MAX) WL ...
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Figure 20: Consecutive WRITE-to-WRITE T0 T1 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Add n DK Notes (or bn) = data-in for bank a (or b) ...
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Figure 21: WRITE-to-READ T0 T1 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Add QK# DK# DK QVLD DQ DM Notes data-in for bank a and address ...
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Figure 22: WRITE-to-READ (Separated by Two NOPs CK# CK COMMAND WRITE NOP Bank a, ADDRESS Add QK# QK DK# DK QVLD DQ DM Notes data-in for bank a and address ...
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Figure 23: WRITE – DM Operation NOP WRITE COMMAND Bank a, ADDRESS Add n DK Notes data-in for bank a and address n. 2. Subsequent elements of ...
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READ Figure 24: Basic READ Burst Timing T0 T1 CK# CK NOP READ COMMAND Bank a ADDRESS Add CKQK (MIN) QK# QK QVLD DQ t CKQK (MAX) QK# QK QVLD DQ Notes data-out ...
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Figure 25: Consecutive READ Bursts ( CK# CK COMMAND READ Bank a ADDRESS Add n QVLD QK Notes ( cn) = data-out from bank a (or bank b or bank ...
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Figure 27: READ-to-WRITE T0 T1 CK# CK READ NOP COMMAND Bank a, ADDRESS Add n DM QK# QK DK# DK QVLD DQ Notes data-out from bank a and address data-in for ...
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Figure 28: Read Data Valid Window for x9 Device QK0# QK0 t QKQ0 (MAX) 2 DQ0 . . . . . . . . . . . . . . . DQ8 DQ (last valid data) DQ (first valid data) ...
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Figure 29: Read Data Valid Window for x18 Device QK0# QK0 DQ0 . . . . . . . . . . . . . . . DQ8 DQ (last valid data) DQ (first valid data) All DQs and QKs ...
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Figure 30: Read Data Valid Window for x36 Device QK0# QK0 t QKQ0 (MAX) 2 DQ0 . . . . . . . . . . . . . . . DQ17 DQ (last valid data) DQ (first valid data) ...
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AUTO REFRESH Figure 31: AUTO REFRESH Cycle COMMAND ADDRESS BANK DK, DK# Notes: 1. AREFx = AUTO REFRESH command to bank x. 2. ACx = any command to bank x; ACy = any command to bank y. 3. BAx = ...
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On-Die Termination Figure 32: READ Burst with ODT T0 T1 CK# CK COMMAND READ NOP Bank a, ADDRESS Col QK# QK QVLD DQ DQ ODT QK# QK QVLD DQ DQ ODT QK# QK QVLD DQ DQ ...
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Figure 33: READ-NOP-READ with ODT T0 T1 CK# CK COMMAND READ NOP Bank a, ADDRESS Col QK# QK QVLD DQ DQ ODT Notes (or bn) = data-out from bank a (or bank b) ...
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Multiplexed Address Mode Figure 35: Command Description in Multiplexed Address Mode READ CK# CK CS# WE# REF# ADDRESS Ax Ay BANK BA ADDRESS Notes: 1. The minimum setup and hold times of the two address parts are defined PDF: 09005aef80a41b59/Source: ...
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Figure 36: Power-Up/Initialization Sequence in Multiplexed Address Mode V EXT REF CK CKH t CKL DKH t DKL COMMAND NOP ...
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Figure 37: Mode Register Definition in Multiplexed Address Mode M8 Drive Impedance Internal 50Ω 3 (default External (ZQ) Notes: 1. Bits A10–A18 must be set to zero not available. 3. ±30 percent temperature ...
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Address Mapping in Multiplexed Address Mode Table 21: 288Mb Address Mapping in Multiplexed Address Mode Data Burst Width Length Ball A0 x36 x18 ...
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Configuration Tables in Multiplexed Address Mode In multiplexed address mode, the read and write latencies are increased by one clock cycle. However, the RLDRAM cycle time remains the same as when in non-multiplexed address mode. Table 22: Cycle Time and ...
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Figure 39: Consecutive WRITE Bursts with Multiplexed Addressing T0 T1 CK# CK COMMAND WRITE NOP ADDRESS Ax Ay BANK Bank a DK Notes: 1. Data from the second WRITE command to bank a ...
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Figure 40: WRITE-to-READ with Multiplexed Addressing T0 T1 CK# CK COMMAND WRITE NOP ADDRESS BANK Bank a QK# DK# DK QVLD DQ DM Notes data-in for bank ...
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Figure 41: Consecutive READ Bursts with Multiplexed Addressing T0 CK# CK COMMAND READ Ax ADDRESS Bank a BANK QVLD QK Notes data-out from bank a. 2. Nominal conditions are assumed for specifications not defined. ...
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Figure 42: READ-to-WRITE with Multiplexed Addressing T0 T1 CK# CK COMMAND READ NOP ADDRESS Ax Ay BANK Bank a DM QK# QK DK# DK QVLD DQ Notes data-out from bank data-in ...
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IEEE 1149.1 Serial Boundary Scan (JTAG) RLDRAM incorporates a serial boundary-scan test access port (TAP) for the purpose of testing the connectivity of the device once it has been mounted on a printed circuit board (PCB). As the complexity of ...
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Test Data-In (TDI) The TDI ball is used to serially input test instructions and data into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the ...
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Update-DR When the EXTEST instruction is selected, there are latched parallel outputs of the boundary-scan shift register that only change state during the update-DR controller state. Instruction Register States The instruction register states of the TAP controller are similar to ...
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Performing a TAP RESET A reset is performed by forcing TMS HIGH (V RESET does not affect the operation of the RLDRAM and may be performed while the RLDRAM is operating. At power-up, the TAP is reset internally to ensure ...
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TAP Instruction Set Overview Many different instructions (2 combinations used are listed in Table 28 on page 74. These six instructions are described in detail below. The remaining instructions are reserved and should not be used. The TAP controller used ...
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SAMPLE/ PRELOAD instruction. If this is an issue still possible to capture all other signals and simply ignore the value of ...
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Figure 46: TAP Timing Test mode select Test data-in Test data-out Table 23: TAP Input AC Logic Levels +0°C ≤ T ≤ +95°C; +1.7V ≤ Description Input high (logic 1) voltage Input low (logic 0) voltage Notes: 1. ...
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Table 25: TAP DC Electrical Characteristics and Operating Conditions +0°C ≤ T ≤ +95°C; +1.7V ≤ Description Input high (logic 1) voltage Input low (logic 0) voltage Input leakage current Output leakage current Output low voltage Output low ...
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Table 28: Instruction Codes Instruction Code Extest 0000 0000 ID code 0010 0001 0000 0101 Sample/preload Clamp 0000 0111 High-Z 0000 0011 Bypass 1111 1111 Table 29: Boundary Scan (Exit) Order Bit# Ball ...
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Table 29: Boundary Scan (Exit) Order (continued) Bit# Ball 33 T10 34 T10 35 T11 36 T11 37 R10 38 R10 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, ...