SGTL5000 Freescale Semiconductor, Inc, SGTL5000 Datasheet
SGTL5000
Available stocks
Related parts for SGTL5000
SGTL5000 Summary of contents
Page 1
... I/O. Deriving it’s architecture from best in class Freescale integrated products that are currently on the market, the SGTL5000 is able to achieve ultra low power with very high performance and functionality, all in one of the smallest footprints available. Target markets include portable media players, GPS units and smart phones ...
Page 2
... SigmaTel and the SigmaTel logo are trademarks of Freescale, Inc. and may be used to identify Freescale products only. Windows Media and the Windows logo are trademarks or registered trademarks of Microsoft Corporation in the United States and other countries. Other product and company names con- tained herein may be trademarks of their respective owners. 2 Copyright © 2008 Freescale, Inc. All rights reserved. SGTL5000 EA2 DS-0-3 ...
Page 3
... ELECTRICAL SPECIFICATIONS 1.1. Absolute Maximum Ratings Exceeding the absolute maximum ratings shown in Table 1 could cause permanent damage to SGTL5000 and is not recommended. Normal operation is not guaran- teed at the absolute maximum ratings and extended exposure could affect long term reliability. Table 1. Absolute Maximum Ratings ...
Page 4
... SNR THD+N Frequency Response PSRR (200mVp-p @ 1kHz on VDDA) 4 Table 3. Audio Performance Min Typical -70 +/-. -87 -87 +/-. -85 +/-.12 17 100 -80 +/-. -86 +/-.11 96 -84 +/-.11 85 Max Unit Vrms SGTL5000 EA2 DS-0-3 ...
Page 5
... Output Power (-60dB input) SNR THD+N Frequency Response I2S In -> DAC -> Headphone Out - 32 Ohm load Output Power (-60dB input) SNR THD+N Frequency Response I2S In -> DAC -> Headphone Out - 10k Ohm load SGTL5000 EA2 DS-0-3 Table 4. Audio Performance Min Typical 1 10k 90 -72 +/-.11 80 102 -89 -87 +/- ...
Page 6
... Frequency Response PSRR (200mVp-p @ 1kHz on VDDA) 1.3. Timing Specifications 1.3.1. Power Up Timing The SGTL5000 has an internal reset that is deasserted 8 SYS_MCLK cycles after all power rails have been brought up. After this time communication can start.. Symbol Parameter Tpc Time from all supplies powered up and SYS_MCLK present to initial communication * 1uS represents 8 SYS_MCLK cycles at the minimum 8MHz SYS_MCLK ...
Page 7
... I2C CTRL_CLK low time Ti2cclkh I2C CTRL_CLK high time CTRL_CLK Ti2csh CTRL_DATA Figure 2. I2C Timing (CTRL_MODE == 0) 1.3.3. SPI This section provides timing for the SGTL5000 while in SPI mode (CTRL_MODE = =1). Symbol Parameter Fspi_clk SPI Serial Clock Frequency Tspidsu SPI data input setup time SGTL5000 EA2 DS-0-3 Table 6 ...
Page 8
... Ti2s_s I2S setup time 8 Table 7. SPI Bus Timing Min 10 ??? ??? Tcsl 1/Fspi_clk Tspiclkh Tspiclkl Tccs Tspidsu Tspidh Figure 3. SPI Timing Table 1-1. Min ??? 10 Typical Max Unit Tcsh Tcsc Typical Max Unit 96 kHz 32*Flrclk, kHz 64*Flrclk SGTL5000 EA2 DS-0-3 ...
Page 9
... Symbol Parameter Ti2s_h I2S hold time . I2S_SCLK I2S_LRCLK In slave mode I2S_LRCLK In master mode I2S_SCLK I2S_DIN I2S_DOUT I2S_LRCLK SGTL5000 EA2 DS-0-3 Table 1-1. Min 10 Ti2s_s 1/Fsclk Ti2s_d Ti2s_s Ti2s_h Ti2s_d 1/Flrclk Figure 4. I2S Interface Timing SGTL5000 Typical Max Unit ns 9 ...
Page 10
... ADC->I2S) Record (ADC->I2S) Analog playback, CODEC bypassed (LINEIN->HP) Standby, all analog power off 10 Current Consumption (mA) VDDD VDDA VDDIO 2.54 .9 3.59 .9 3.71 1.10 2.29 1.06 1.48 .89 .019 .002 3.01 2.17 Current Consumption (mA) VDDD VDDA VDDIO 3.45 .067 4.49 .067 4.67 .343 2.90 .296 1.91 .039 .04 .002 Power(mW) 6.19 8.08 8.67 6.02 4.27 .038 9.31 Power(mW) 11.60 15.03 16.53 10.56 6.43 .139 SGTL5000 EA2 DS-0-3 ...
Page 11
... Table 9: Power Consumption: VDDA=3.3V, VDDIO=3.3V Mode Playback with PLL (I2S->DAC->HP) SGTL5000 EA2 DS-0-3 Current Consumption (mA) VDDD VDDA VDDIO 3.92 2.76 SGTL5000 Power(mW) 22.05 11 ...
Page 12
... SGTL5000 3. PINOUT & PACKAGE INFO 3.1. Pinout 12 20QFN Pinout HP_R I2S_SCLK 2 HP_VGND I2S_LRCLK 3 VDDA SYS_MCLK 4 HP_L VDDIO 5 VAG MIC_BIAS GND Figure 5. SGTL5000 20QFN Pinout SGTL5000_20QFN SGTL5000_20QFN GND I2S_SCLK 2 HP_R I2S_LRCLK 3 GND 4 HP_VGND SYS_MCLK 5 VDDA 6 HP_L 7 AGND CPFILT 8 NC Figure 6. SGTL5000 32QFN Pinout ...
Page 13
... I2S_DOUT 17 I2S_DIN 18 CTRL_DATA 19 CTRL_CLK 20 VDDD PAD GND SGTL5000 EA2 DS-0-3 Table 10. 20 pin QFN pinout Description Right headphone output Headphone virtual ground Analog voltage Left headphone output DAC VAG filter Right line out Left line out Right line in Left line in Microphone input ...
Page 14
... System master clock No Connect I2S frame clock I2S bit clock I2S data output I2S data input Notes GROUND ANALOG GROUND ANALOG POWER ANALOG GROUND DIGITAL DIGITAL ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG POWER DIGITAL DIGITAL DIGITAL DIGITAL DIGITAL SGTL5000 EA2 DS-0-3 ...
Page 15
... VDDD 31 CTRL_ADR0_CS 32 CTRL_MODE PAD GND 3.3. Package SGTL5000 EA2 DS-0-3 Table 11. 32 pin QFN pinout Description I2C Mode: Serial Data (SDA); SPI Mode: Serial Data Input (MOSI) No connect I2C Mode: Serial Clock (SCL); SPI Mode: Serial Clock (SCK) Digital voltage I2C Mode: I2C Address Select 0; ...
Page 16
... SGTL5000 16 SGTL5000 EA2 DS-0-3 ...
Page 17
... SGTL5000 EA2 DS-0-3 SGTL5000 17 ...
Page 18
... SGTL5000 18 SGTL5000 EA2 DS-0-3 ...
Page 19
... TYPICAL CONNECTION DIAGRAMS Typical connection diagrams are shown in this section that demonstrate the flexibil- ity of the SGTL5000. Both low cost and low power configurations are presented although it should be noted that all configurations offer a low cost design with high performance and low power. ...
Page 20
... LINE_OUT_RIGHT LINE_IN_LEFT C? C? 1uF 1uF C? C? 1uF 1uF LINE_OUT_LEFT LINE_IN_RIGHT I2C_CLK I2C_DATA I2S_DIN I2SDOUT I2S_SCLK I2S_LRCLK SYS_MCLK VDDIO (1.62V to 3.6V .1uF .1uF 2.2k 2.2k 2.2k 2.2k .1uF .1uF MIC MIC + + 10uF 10uF C? C? 0.1uF 0.1uF 6.3V 6. SGTL5000 EA2 DS-0-3 ...
Page 21
... C3 C3 220uF 220uF Audio Jack Audio Jack VDDA (=1.6V 0.1uF 0.1uF C6 C6 .1uF .1uF LINE_OUT_RIGHT LINE_OUT_LEFT 20QFN Typical Connection Diagram - Lowest Power Configuration SGTL5000 EA2 DS-0-3 VDDD (=1.2V 0.1uF 0.1uF HP_R I2S_SCLK 2 14 HP_VGND I2S_LRCLK 3 13 VDDA SYS_MCLK 4 12 ...
Page 22
... GND Solder Pad to GND 0.1uF 0.1uF 1uF 1uF C5 C5 1uF 1uF C6 C6 1uF 1uF C7 C7 1uF 1uF C8 C8 1uF 1uF CTRL_CLK 6,7 CTRL_DATA 6,7 I2S_DIN 7 I2S_DOUT 7 I2S_SCLK 7 I2S_LRCLK 7 SYS_MCLK VDD (=3.1V to 3.6V .1uF .1uF MIC MIC LINE_IN_L 4 LINE_IN_R 4 SGTL5000 EA2 DS-0-3 ...
Page 23
... C3 C3 220uF 220uF Audio Jack Audio Jack VDDA (=1.6V 0.1uF 0.1uF 5 LINE_OUT_R 5 LINE_OUT_L 32QFN Typical Connection Diagram - Lowest Power Configuration SGTL5000 EA2 DS-0-3 VDDD (=1.2V 0.1uF 0.1uF GND I2S_SCLK 2 HP_R I2S_LRCLK 3 GND NC 4 HP_VGND SYS_MCLK 5 VDDA VDDIO 6 HP_L ...
Page 24
... C13 1uF 1uF LINE_IN_RIGHT 1. VDDD is driven externally by 1.2V supply. 2. VDDA is driven at 1.6V 3. VDDIO is driven at 3.1V I2C_CLK I2C_DATA I2S_DIN I2SDOUT I2S_SCLK I2S_LRCLK SYS_MCLK VDDIO (=3.1V .1uF .1uF 2.2k 2.2k 2.2k 2.2k .1uF .1uF C11 C11 MIC MIC + + 10uF 10uF C8 C8 0.1uF 0.1uF 6.3V 6.3V SGTL5000 EA2 DS-0-3 ...
Page 25
... AGND (pin 7) should be "star" connected to the jack grounds for line in and line out and the ground side of the capacitor tied to VAG. This node should via to the ground plane (or connected to ground single A point SGTL5000 EA2 DS-0-3 3 VDDD C? C? 0.1uF 0.1uF U? U? ...
Page 26
... Tone Control, parametric equalizer, and graphic equalizer The SGTL5000 can accept an external standard master clock at a multiple of the sampling frequency (i.e. 256*Fs, 385*Fs, 512*Fs). In addition it can take non stan- dard frequencies and use the internal PLL to derive the audio clocks. The device 8kHz, 11 ...
Page 27
... To guarantee against clipping it is important that the gain in a signal path in addition to the signal level does not exceed 0dB at any point. 5.2. Power The SGTL5000 has a flexible power architecture to allow the system designer to minimize power consumption and maximize performance at the lowest cost. 5.2.1. External Power Supplies The SGTL5000 requires 2 external power supplies: VDDA and VDDIO ...
Page 28
... For most applications a lower voltage can be used for the best performance/power combination. 5.3. Reset The SGTL5000 has an internal reset that is deasserted 8 SYS_MCLKs after all power rails have been brought up. After this time communication can start. See sec- tion 1.3 for timing specification. 28 ...
Page 29
... Using the PLL - Asynchronous SYS_MCLK input An integrated PLL is provided in the SGTL5000 that allows any clock from 8MHz to 27MHz to be connected to SYS_MCLK. This can help save system costs as a clock available elsewhere in the system can be used to derive all audio clocks using the internal PLL ...
Page 30
... Processing, for DAP information and configuration. It should be noted that the analog bypass from Line input to headphone output does not go through the audio switch. 30 SYS_MCLK>17MHz? Yes No CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0 PLL_INPUT_FREQ = SYS_MCLK Sampling Yes Frequency = No 44.1kHz? PLL_OUTPUT_FREQ=196 .608 MHz Figure 11. PLL Programming Flowchart SGTL5000 EA2 DS-0-3 ...
Page 31
... Values of 0dB, +20dB, +30dB and +40dB are available. 5.6.3. ADC The SGTL5000 contains an ADC who takes its input from either the line input or a microphone. The register field CHIP_ANA_CTRL->SELECT_ADC controls this selection. The output of the ADC feeds the audio switch. ...
Page 32
... Analog Outputs The SGTL5000 contains a single stereo DAC that can be used to drive a heapdhone output and a line output. The DAC receives its input from the audio switch. The headphone output and the line output can be driven at the same time from the DAC. ...
Page 33
... The I2S_LRCLK and I2S_SCLK can be programmed as master (driven to an exter- nal target) or slave (driven from an external source). When the clocks are in slave mode, they must be synchronous to SYS_MCLK. For this reason the SGTL5000 can only operate in synchronous mode (see section 5.4) while in I2S slave mode. ...
Page 34
... The data and frame clock may be config- ured to clock in on the rising or falling edge of Bit Clock L01 L00 (n- (n- R01 R00 (n- (n- SGTL5000 EA2 DS-0-3 ...
Page 35
... Digital Audio Processing The SGTL5000 contains a digital audio processing block (DAP) attached to the source select switch. The digitized signal from the source select switch can be routed into the DAP block for audio processing. The DAP has the following 5 sub blocks: • ...
Page 36
... The dual input digital mixer allows for two incoming streams from the source select switch as shown in Figure 15. 36 Parametric SigmaTel SigmaTel Bass Graphic Surround Enhance Only one of PEQ/GEQ/TC can be used at a time 7-Band EQ To 5-Band Source Select EQ Swtich Tone Control SGTL5000 EA2 DS-0-3 ...
Page 37
... The SGTL Surround can be enabled or configured in pass-through mode (input will be passed through without any processing). When enabling the Surround, mono or stereo input type must be selected based on the input signal. Surround width may be adjusted for the size of the sound stage. SGTL5000 EA2 DS-0-3 Main Channel Volume Sum Mix Channel Volume DAP_MIX_CHAN-> ...
Page 38
... Tone Control (Bass and Treble control) blocks are implemented as mutually exclusive blocks. Only one block can be used at a given time. Please refer to section 6.2.4.4 for a programming example that shows how to select the desired EQ mode. 38 DAP_BASS_ENHANCE_CTRL ->LR_LEVEL DAP_BASS_ENHANCE_CTRL ->CUTOFF_HPF ->BYPASS_HPF High Pass Filter DAP_BASS_ENHANCE_CTRL ->BASS_LEVEL Output (To PEQ/GEQ/TC) SGTL5000 EA2 DS-0-3 ...
Page 39
... Note that coefficients are sample-rate dependent and separate coefficients must be gen- erated for different sample rates. Please contact Freescale for assistance with gen- erating the coefficients. SGTL5000 EA2 DS-0-3 7-Band Parametric EQ − − ...
Page 40
... Figure 18 shows the AVC block diagram and controls. DAP_AVC_THRESHOLD Input from Threshold Dual Input Mixer Level Compare 40 5-Band Graphic EQ Tone Control If < Threshold Decay (0.05dB/s to ~200dB/s) DAP_AVC_DECAY DAP_AVC_THRESHOLD -> MAX_GAIN Volume Control If > Threshold Attack (0.8dB/s to ~3200dB/s) DAP_AVC_ATTACK Figure 18. DAP AVC Block Diagram Output To SGTL Surround SGTL5000 EA2 DS-0-3 ...
Page 41
... I2C_ADR0_CS and R/W is the read/write bit from the I2C protocol. For the 20QFN version of the SGTL5000 the I2C address is always 0001010(R/W). The SGTL5000 is always the slave on all transactions which means that an external master will always drive CTRL_CLK. In general an I2C transaction looks as follows. ...
Page 42
... The following diagrams describe the different access formats. The gray fields are from the I2C master, and the white fields are the SGTL5000 responses. Data[n] cor- responds to the data read from the address sent, data[n+1] is the data from the next register, and so on ...
Page 43
... Figure 20 below shows the functional timing diagram of the SPI communication pro- tocol as supported by SGTL5000 chip. Note that on the rising edge of the SS, the chip latches to previous 32 bits of data. It interprets the latest 16-bits as register value and 16-bits preceding it as register address. ...
Page 44
... ReadRegister( usRegister, &usData ); // 2) Clear out old bits usData = usData & usClearMask set new bit values usData = usData | usSetValue Write out new value created WriteRegister( usRegister, usData ); } 44 REGISTERVALUE BITFIELDVALUE //Bitfield Location unsigned short usClearMask, unsigned short usSetValue ) All Also, the SGTL5000 EA2 DS-0-3 ...
Page 45
... Configure slow ramp up rate to minimize pop (bit 0) Write CHIP_REF_CTRL // Enable short detect mode for headphone left/right // and center channel and set short detect current trip level SGTL5000 EA2 DS-0-3 Chip Powerup and Supply Configurations The initialization sequence below assumes VDDIO = 3.3V and 0x0008 ...
Page 46
... Sys_MCLK_Input_Freq = Sys_MCLK_Input_Freq/2; // PLL output frequency is different based on the sample clock // rate used. if (Sys_Fs_Rate == 44.1kHz) PLL_Output_Freq = 180.6336MHz else PLL_Output_Freq = 196.608MHz 46 0x1106 0x0133 0x6AFF 0x0073 0x0505 System MCLK and Sample Clock // bits 3:2 // bits 1:0 0x0001 // bit 7 0x0001 0x0001 // bit 10 // bit 8 0x0001 // bit 3 SGTL5000 EA2 DS-0-3 ...
Page 47
... Enable Dual Input Mixer Modify DAP_CONTROL->MIX_EN 0x0001 // NOTE: This example assumes mix level of main and mix // channels as 100% and 50% respectively // Configure main channel volume to 100% (No change from input // level) SGTL5000 EA2 DS-0-3 I2S_IN -> DAP -> DAC -> LINEOUT, HP_OUT // bits 7:6 // bits 5:4 // bit 6 MIC_IN -> ADC -> I2S_OUT ...
Page 48
... Select 7-Band PEQ mode and enable 7 PEQ filters Write DAP_AUDIO_EQ 0x0001 Write DAP_PEQ 0x0007 // Tone Control mode Write DAP_AUDIO_EQ 0x0002 // 5-Band GEQ Mode Write DAP_AUDIO_EQ 0x0003 48 SigmaTel Surround SigmaTel Bass Enhance 7-Band Parametric EQ / 5-Band Graphic EQ / Tone Control This example shows // bits 6:4 // bits 7:4 // bits 6:0 SGTL5000 EA2 DS-0-3 ...
Page 49
... Write CHIP_ANA_HP_CTRL usCurrentVol LINEOUT and DAC volume control Modify CHIP_ANA_CTRL->MUTE_LO 0x0000 // Configure DAC left and right digital volume. // volume of 0dB SGTL5000 EA2 DS-0-3 Automatic Volume Control (AVC) This can be modified by setting various bit-fields in Example shows gain of 20dB // bits 1:0 // bit 5 // bit 8 ...
Page 50
... GEQ Volume Change This programming example shows how to program the GEQ volume when end-user changes the volume on any of the 5 bands bit 2 // bit 3 // bit 0 Repeat this for all enabled usB0MSB[i] usB0LSB[i] usB1MSB[i] usB1LSB[i] usB2MSB[i] usB2LSB[i] usA1MSB[i] usA1LSB[i] usA2MSB[i] usA2LSB[i] // bit 8 SGTL5000 EA2 DS-0-3 ...
Page 51
... Write DAP_AUDIO_EQ_TREBLE_BAND4 usCurrentVal; } 6.3.5. SigmaTel Surround On/Off This programming example shows how to program the Surround when end-user turns it on/off on his device. The Surround width should be ramped up to highest value before enabling/disabling the Surround to avoid any pops. SGTL5000 EA2 DS-0-3 SGTL5000 51 ...
Page 52
... Ramp Bass level to lowest bass (lowest bass = 0x007F) usNumSteps = abs(0x007F - usOriginalVal); for (int i++; usNumSteps ) { ++usNextVal; Modify DAP_BASS_ENHANCE_CTRL->BASS_LEVEL usNextVal Enable (To disable, write 0x0000) Bass Enhance // EN bit 0 Modify DAP_BASS_ENHANCE->EN 0x0001; // Ramp Bass level back to original value for (int i++; usNumSteps ) { --usNextVal; Modify DAP_BASS_ENHANCE_CTRL->BASS_LEVEL usNextVal SGTL5000 EA2 DS-0-3 ...
Page 53
... Automatic Volume Control (AVC) On/Off This programming example shows how to program the AVC on/off when end-user turns it on/off on his device. // Enable AVC (To disable, write 0x0000) Modify DAP_AVC_CTRL->EN 0x0001 SGTL5000 EA2 DS-0-3 SGTL5000 // bit 0 53 ...
Page 54
... I2S_OUT_POWE RUP 0 I2S_IN_POWERU P 54 CHIP_ID 0x0000 RESET RO 0xA0 SGTL5000 Part ID 0xA0 - 8 bit identifier for SGTL5000 0x00 SGTL5000 Revision ID RO 0xHH - revision number for SGTL5000. CHIP_DIG_POWER 0x0002 RESET RO 0x0 Reserved RW 0x0 Enable/disable the ADC block, both digital and analog ...
Page 55
... FIELD 15:6 RSVD 5:4 RATE_MODE 3:2 SYS_FS 1:0 MCLK_FREQ 7.0.0. BITS FIELD 15:9 RSVD SGTL5000 EA2 DS-0-3 CHIP_CLK_CTRL 0x0004 RESET RO 0x0 Reserved 0x0 Sets the sample rate mode. MCLK_FREQ is still specified RW relative to the rate in SYS_FS 0x0 = SYS_FS specifies the rate 0x1 = Rate is 1/2 of the SYS_FS rate ...
Page 56
... Slave: I2S_LRCLK and I2S_SCLK are inputs 0x1 = Master: I2S_LRCLK and I2S_SCLK are outputs NOTE: If the PLL is used (CHIP_CLK_CTRL- >MCLK_FREQ==0x3), the SGTL5000 must be a master of the I2S port (MS==1) 0x0 Sets the edge that data (input and output) is clocked in on for ...
Page 57
... DAP_SELECT 5:4 DAC_SELECT 3:2 RSVD 1:0 I2S_SELECT 7.0.0. SGTL5000 EA2 DS-0-3 RW RESET 0x0 DAP Mixer Input Swap RW 0x0 = Normal Operation 0x1 = Left and Right channels for the DAP MIXER Input will be swapped. RW 0x0 DAP Input Swap 0x0 = Normal Operation 0x1 = Left and Right channels for the DAP Input will be ...
Page 58
... Freeze the ADC high-pass filter offset register. The offset will continue to be subtracted from the ADC data stream. RW 0x0 ADC High Pass Filter Bypass 0x0 = Normal operation 0x1 = Bypassed and offset not updated CHIP_DAC_VOL 0x0010 DEFINITION SGTL5000 EA2 DS-0-3 ...
Page 59
... BITS FIELD 15:14 RSVD 9:8 I2S_LRCLK 7:6 I2S_SCLK SGTL5000 EA2 DS-0-3 RW RESET 0x3C DAC Right Channel Volume RW Set the Right channel DAC volume with 0.5017 dB steps from 0 to -90 dB 0x3B and less = Reserved 0x3C = 0 dB 0x3D = -0.5 dB 0xF0 = -90 dB 0xFC and greater = Muted If VOL_RAMP_EN = 1, there will be an automatic ramp to the new volume setting ...
Page 60
... ADC Right Channel Volume RW Right channel analog ADC volume control in 1.5dB steps. 0x0 = 0dB 0x1 = +1.5dB ... 0xF = +22.5dB This range will be -6dB to +16.5dB if ADC_VOL_M6DB is set to 1. DEFINITION 2.5V 3.3V 2.87 mA 4.02 mA 5.74 mA 8.03 mA 8.61 mA 12.05 mA 2.5V 3.3V 2.87 mA 4.02 mA 5.74 mA 8.03 mA 8.61 mA 12.05 mA 2.5V 3.3V 2.87 mA 4.02 mA 5.74 mA 8.03 mA 8.61 mA 12. DEFINITION SGTL5000 EA2 DS-0-3 ...
Page 61
... This is an analog control register that includes mutes, input selects, and zero-cross- detectors for the ADC, headphone, and lineout SGTL5000 EA2 DS-0-3 RW RESET 0x0 ADC Left Channel Volume RW Left channel analog ADC volume control in 1.5dB steps. 0x0 = 0dB 0x1 = +1.5dB ...
Page 62
... ADC ZCD disabled 0x1 = ADC ZCD enabled RW 0x1 Mute the ADC analog volume 0x0 = Unmute 0x1 = Mute 0x0026 RESET 0x0 Reserved RO 0x0 Determines chargepump source when VDDC_ASSN_OVRD RW is set. 0x0 = VDDA 0x1 = VDDIO DEFINITION DEFINITION SGTL5000 EA2 DS-0-3 ...
Page 63
... BITS FIELD 15:9 RSVD 8:4 VAG_VAL 3:1 BIAS_CTRL 0 SMALL_POP SGTL5000 EA2 DS-0-3 RW RESET 0x0 Chargepump Source Assignment Override RW 0x0 = Chargepump source is automatically assigned based on higher of VDDA and VDDIO 0x1 = the source of chargepump is manually assigned by VDDC_MAN_ASSN If VDDIO and VDDA are both the same and greater than 3 ...
Page 64
... Sets the microphone amplifier gain. At 0dB setting the THD can be slightly higher than other paths- typically around ~65dB. At other gain settings the THD will be better. 0x0 = 0dB 0x1 = +20dB 0x2 = +30dB 0x3 = +40dB 0x002C DEFINITION SGTL5000 EA2 DS-0-3 ...
Page 65
... BITS FIELD 15:13 RSVD 12:8 LO_VOL_RIGHT 7:5 RSVD 4:0 LO_VOL_LEFT SGTL5000 EA2 DS-0-3 RW RESET 0x0 Reserved RO RW 0x0 Controls the output bias current for the lineout amplifiers. The nominal recommended setting for a 10kohm load with 1nF load cap is 0x3. There are only 5 valid settings. 0x0=0.18mA, 0x1=0.27mA, 0x3=0.36mA, 0x7=0.45mA, 0xF=0 ...
Page 66
... Power down 0x1 = Power up 0x1 Power up the circuitry needed during the power up ramp and RW reset. After reset this bit can be cleared if VDDD is coming from an external source. 0x0 = Power down 0x1 = Power up LO_VOL_* 0x06 0x0F 0x19 0x0F DEFINITION SGTL5000 EA2 DS-0-3 ...
Page 67
... HEADPHONE_P OWERUP 3 DAC_POWERUP 2 CAPLESS_HEAD PHONE_POWER UP SGTL5000 EA2 DS-0-3 RW RESET 0x0 Power up the VDDC chargepump block. If neither VDDA or RW VDDIO larger this bit should be cleared before analog blocks are powered up. 0x0 = Power down 0x1 = Power up Note that for charge pump to function, either the PLL must be powered on and programmed correctly (refer to CHIP_CLK_CTRL-> ...
Page 68
... PLL_OUTPUT_FREQ = 180.6336 MHz if System sample rate = 44.1 KHz else PLL_OUTPUT_FREQ = 196.608 MHz if System sample rate != 44.1 KHz INPUT_FREQ = Frequency of the external MCLK provided if CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x0 else INPUT_FREQ = (Frequency of the external MCLK provided/2) If CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x1 DEFINITION DEFINITION SGTL5000 EA2 DS-0-3 ...
Page 69
... Status bits for analog blocks BITS FIELD 15:10 RSVD 9 LRSHORT_STS 8 CSHORT_STS 7:5 RSVD SGTL5000 EA2 DS-0-3 0x0034 RESET RO 0x0 Reserved 0x0 Setting this bit enables an internal oscillator to be used for the RW zero cross detectors, the short detect recovery, and the charge pump ...
Page 70
... Put ADCmux output onto the headphone output pin. Must remove headphone load and any external headphone compensation for this mode. 0x0 Enable headphone common to be used in ADCmux for testing RW 0x0 Enable the mic-adc-dac-HP path DEFINITION DEFINITION SGTL5000 EA2 DS-0-3 ...
Page 71
... INVERT_DAC_D ATA_TIMING 7 DAC_EXTEND_R TZ 6 DAC_DOUBLE_I 5 DAC_DIS_RTZ 4 DAC_CLASSA 3 INVERT_ADC_SA MPLE_CLOCK 2 INVERT_ADC_D ATA_TIMING 1 ADC_LESSI SGTL5000 EA2 DS-0-3 RW RESET 0x0 Enable the analog testmode paths RW 0x003A RESET RO 0x0 Reserved RW 0x0 Changes the lineout amplifier power supply from VDDIO to VDDA. Typically lineout should be on the higher power supply ...
Page 72
... This short detect trip point is also effected by the bias current adjustments made by CHIP_REF_CTRL -> BIAS_CTRL and by CHIP_ANA_TEST1 -> HP_IALL_ADJ. 0x3=25mA 0x2=50mA 0x1=75mA 0x0=100mA 0x4=125mA 0x5=150mA 0x6=175mA 0x7=200mA 0x0 Reserved RO DEFINITION DEFINITION SGTL5000 EA2 DS-0-3 ...
Page 73
... FIELD 6:4 LVLADJC 3:2 MODE_LR 1:0 MODE_CM SGTL5000 EA2 DS-0-3 RW RESET 0x0 These bits adjust the sensitivity of the capless headphone RW center channel short detector in 50mA steps. This trip point can vary by ~30% over process so leave plenty of guardband to avoid false trips. This short detect trip point is also effected by the bias current adjustments CHIP_REF_CTRL -> ...
Page 74
... Disabled 0x1 = 1 Filter Enabled 0x2 = 2 Filters Enabled ..... 0x7 = Cascaded 7 Filters DAP_AUDIO_EQ->EN bit must be set order to enable the PEQ 0x0104 RESET 0x0 Reserved DEFINITION DEFINITION DEFINITION SGTL5000 EA2 DS-0-3 ...
Page 75
... RSVD 13:8 LR_LEVEL 7 RSVD 6:0 BASS_LEVEL 7.0.0.28. DAP_AUDIO_EQ BITS FIELD 15:2 RSVD SGTL5000 EA2 DS-0-3 RW RESET 0x0 Bypass high pass filter RW 0x0 = Enable high pass filter 0x1 = Bypass high pass filter RO 0x0 Reserved RW 0x4 Set cut-off frequency 0x0 = 80 Hz 0x1 = 100 Hz 0x2 = 125 Hz 0x3 = 150 Hz ...
Page 76
... Stereo input Enable RESET 0x0 Reserved RO 0x0 When set, the coefficients written in the ten coefficient data WO registers will be loaded into the filter specified by INDEX DEFINITION 0x010A DEFINITION 0x010C DEFINITION SGTL5000 EA2 DS-0-3 ...
Page 77
... BIT_8 3 BIT_7 2 BIT_6 1 BIT_5 SGTL5000 EA2 DS-0-3 RW RESET 0x0 Specifies the index for each of the seven bands of the filter RW coefficient that needs to be written to. Each filter has 5 coefficients that need to be loaded into the 10 coefficient registers (MSB,LSB) before setting the index and WR bit. ...
Page 78
... Each LSB is 0.25dB. To convert dB to hex value, use: Hex Value = 4*dBValue + RESET RO 0x0 Reserved DEFINITION 0x0110 DEFINITION 0x0116 DEFINITION 0x0118 DEFINITION SGTL5000 EA2 DS-0-3 ...
Page 79
... BITS FIELD 15:7 RSVD 6:0 VOLUME 7.0.0.37. DAP_AUDIO_EQ_TREBLE_BAND4 9900Hz SGTL5000 EA2 DS-0-3 RW RESET 0x2F Sets GEQ Band1 RW 0x5F = sets to 12dB 0x2F = sets to 0dB 0x00 = sets to -12dB Each LSB is 0.25dB. To convert dB to hex value, use: Hex Value = 4*dBValue + RESET ...
Page 80
... RW RESET 0x0000 DAP Mix Channel Volume RW 0xFFFF = 200% 0x8000 = 100% 0x0000 (default 0x0124 RESET RO 0x0 Reserved RW 0x1 Reserved. DEFINITION DEFINITION DEFINITION DEFINITION SGTL5000 EA2 DS-0-3 ...
Page 81
... BITS FIELD 15:0 THRESH 7.0.0.42. DAP_AVC_ATTACK BITS FIELD 15:12 RSVD SGTL5000 EA2 DS-0-3 RW RESET 0x1 Maximum gain that can be applied by the AVC in expander RW mode. 0x0 = 0dB gain 0x1 = 6dB of gain 0x2 = 12dB of gain 0x0 Reserved RO 0x1 Integrator Response RW 0x0 = 0mS LBI 0x1 = 25mS LBI ...
Page 82
... SYS_FS is the system sample rate configured in CHIP_CLK_CTRL register. Example values: 0x284 = 32dB/s 0xA0 = 8dB/s 0x50 = 4dB/s 0x28 = 2dB RESET RW 0x0 Most significant 16-bits of the 20-bit filter coefficient that needs to be written DEFINITION DEFINITION 0x012C DEFINITION SGTL5000 EA2 DS-0-3 ...
Page 83
... BITS FIELD 15:0 MSB 7.0.0.47. DAP_COEF_WR_B2_LSB BITS FIELD 15:4 RSVD 3:0 LSB 7.0.0.48. DAP_COEF_WR_A1_MSB BITS FIELD 15:0 MSB SGTL5000 EA2 DS-0 RESET RO 0x0 Reserved RW 0x0 Least significant 4 bits of the 20-bit filter coefficient that needs to be written RESET RW 0x0 ...
Page 84
... Most significant 16-bits of the 20-bit filter coefficient that needs to be written RESET 0x0 Reserved RO 0x0 Least significant 4 bits of the 20-bit filter coefficient that needs written. 0x0136 DEFINITION 0x0138 DEFINITION 0x013A DEFINITION SGTL5000 EA2 DS-0-3 ...