MT49H16M18CBM-33 Micron Semiconductor Products, MT49H16M18CBM-33 Datasheet
MT49H16M18CBM-33
Specifications of MT49H16M18CBM-33
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MT49H16M18CBM-33 Summary of contents
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SIO RLDRAM MT49H16M18C – 16 Meg banks Features • 400 MHz DDR operation (800 Mb/s/pin data rate) • 28.8 Gb/s peak bandwidth (x18 at 400 MHz clock frequency) • Organization – 16 Meg x 18 separate ...
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Figure 2: 288Mb RLDRAM II SIO Part Numbers Configuration 16 Meg x 18 Notes: 1. The FBGA package is being phased out. BGA Part Marking Decoder Due to space limitations, BGA-packaged components have an abbreviated part marking that is different ...
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Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: 16 Meg x 18 Ball Assignments (Top View) 144-Ball µBGA/FBGA . . . . . . . . . . . . . . . . . . . . . . . . . ...
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General Description The Micron designed for high bandwidth data storage—telecommunications, networking, and cache applications, etc. The chip’s 8-bank architecture is optimized for sustainable high speed operation. The double data rate (DDR) separate I/O interface transfers two data words per clock ...
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Figure 3: State Diagram WRITE MRS PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_D2.fm - Rev. O 6/08 EN 288Mb: x18 2. 1.8V V EXT Initialization sequence DSEL/NOP Automatic sequence Command sequence Micron Technology, Inc., reserves the right to change products or ...
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Functional Block Diagrams Figure 4: 16 Meg x 18 Functional Block Diagram ZQ ODT control CK CK# Control CS# logic REF# WE# Refresh 13 counter Mode register Row- address MUX A0–A19 Address 23 BA0–BA2 register 3 1 ...
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Ball Assignments and Descriptions Table 1: 16 Meg x 18 Ball Assignments (Top View) 144-Ball µBGA/FBGA REF SS EXT A22 D6 Q6 ...
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Table 2: Ball Descriptions Symbol Type A0–A19 Input Address inputs: A0–A19 define the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising ...
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Package Dimensions Figure 5: 144-Ball µBGA 10.70 CTR SEATING PLANE 2.41 CTR A 0.08 A 144X Ø 0.45 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE BALL A12 PRE-REFLOW BALL MOLD DIAMETER IS 0. COMPOUND 0.40 SMD BALL ...
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Figure 6: 144-Ball FBGA SEATING PLANE A 0.10 A 144X Ø 0.55 DIMENSIONS APPLY TO SOLDER BALLS POST MOLD REFLOW. THE PRE-REFLOW COMPOUND BALL IS Ø0. Ø0.40 NSMD BALL PAD. BALL A12 17.00 8.50 4.40 Notes: 1. All ...
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Electrical Specifications – I Table 3: I Operating Conditions and Maximum Limits DD Description Conditions t Standby current CK = Idle; All banks idle; No inputs toggling t Active standby CK = MIN, CS commands; Bank current ...
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Floating is defined as inputs at V 4e. Continuous data is defined as half the signals changing between HIGH and LOW 4f. Continuous address is defined as half the address signals changing between HIGH and 4g. ...
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Electrical Specifications – AC and DC Absolute Maximum Ratings Stresses greater than those listed in Table 4 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any ...
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On-die termination may be selected using mode register bit 9 (see Figure 11 on page 28). A resistance device, I 10. If MRS bit use RQ = ...
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Table 7: Differential Input Clock Operating Conditions Notes 1–4 apply to the entire table; Unless otherwise noted: +0°C ≤ T Parameter/Condition Clock input voltage level: CK and CK# Clock input differential voltage: CK and CK# Clock input differential voltage: CK ...
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Input Slew Rate Derating Table 8 on page 19 and Table 9 on page 20 define the address, command, and data setup and hold derating values. These values are added to the default t t CH/ 2 V/ns the nominal ...
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Table 8: Address and Command Setup and Hold Derating Values Command Address Slew AS REF Rate (V/ns) CK/CK# Crossing 2.0 0 1.9 5 1.8 11 1.7 18 1.6 25 1.5 33 1.4 43 1.3 54 1.2 ...
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Table 9: Data Setup and Hold Derating Values t Data Slew Rate REF (V/ns) CK/CK# Crossing 2.0 0 1.9 5 1.8 11 1.7 18 1.6 25 1.5 33 1.4 43 1.3 54 1.2 67 1.1 82 1.0 ...
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Figure 8: Nominal AS/ CS/ Table 10: Capacitance Description Address/control input capacitance Input/output capacitance (D, Q, DM, and QK/QK#) Clock capacitance (CK/CK#, and DK/DK#) JTAG pins Notes: 1. Capacitance is not tested on ZQ pin. 2. JTAG pins ...
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Table 11: AC Electrical Characteristics Notes 1–4 (page 23) apply to the entire table Description Symbol Clock Input clock cycle time Input data clock cycle time Clock jitter: period Clock jitter: cycle-to-cycle t Clock HIGH time CKH, t Clock LOW ...
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Notes 1. All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK# and to the crossing point with V 2. Outputs measured with equivalent load: 3. Tests for AC timing nominal reference/supply voltage levels, but ...
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Temperature and Thermal Impedance It is imperative that the RLDRAM device’s temperature specifications, shown in Table 12, be maintained in order to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step ...
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Table 13: Thermal Impedance θ JA (°C/W) Package Substrate Airflow = 0m/s µBGA 2-layer 4-layer FBGA 2-layer 4-layer Notes: 1. Thermal impedance data is based on a number of samples from multiple lots and should be viewed as a typical ...
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Commands The following table provides descriptions of the valid commands of the RLDRAM. All input states or sequences not shown are illegal or reserved. All command and address inputs must meet setup and hold times around the rising edge of ...
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MODE REGISTER SET (MRS) The mode register set stores the data for controlling the operating modes of the memory. It programs the RLDRAM configuration, burst length, test mode, and I/O options. During an MRS command, the address inputs A0–A17 are ...
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Figure 11: Mode Register Definition in Nonmultiplexed Address Mode On-Die Termination Internal 50Ω 6 (default Notes: 1. A10–A17 must be set to zero; A18–An = “Don’t Care.” not used in MRS. 3. ...
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Configuration Tables Table 16 shows the different configurations that can be programmed into the mode register. The WRITE latency is equal to the READ latency plus one in each configuration in order to maximize data bus utilization. Bits M0, M1, ...
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Figure 12: Read Burst Lengths T0 T1 CK# CK COMMAND READ NOP Bank a, ADDRESS Col QK# QK QVLD Q QK# QK QVLD Q QK# QK QVLD Q Notes data-out from bank ...
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setting since the device requires two clocks to read and write the data. The bank addresses are delivered to the RLDRAM at the same time as the WRITE and READ command and the ...
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Table 18: On-Die Termination DC Parameters Description Termination voltage On-die termination Notes: 1. All voltages referenced The R Figure 13: On-Die Termination-Equivalent Circuit D PDF: 09005aef815b2df8/Source: 09005aef811ba111 288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 6/08 EN 288Mb: ...
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WRITE Write accesses are initiated with a WRITE command, as shown in Figure 14. The address needs to be provided during the WRITE command. During WRITE commands, data will be registered at both edges of DK according to the programmed ...
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READ Read accesses are initiated with a READ command, as shown in Figure 15. Addresses are provided with the READ command. During READ bursts, the memory device drives the read data edge-aligned with the QKx signals. After ...
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AUTO REFRESH (AREF) AREF is used to perform a REFRESH cycle on one row in a specific bank. Because the row addresses are generated by an internal refresh counter for each bank, the external address balls are “Don’t Care.” The ...
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Operations INITIALIZATION The RLDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operations or permanent damage to the device. The following sequence is used for power-up: 1. Apply ...
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Figure 17: Power-Up/Initialization Sequence V EXT REF CK CKH t CKL DKH t DKL COMMAND NOP NOP DM ADDRESS BANK ADDRESS ...
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Figure 18: Power-Up/Initialization Flow Chart Step Notes: 1. The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 ...
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WRITE Figure 19: WRITE Burst T0 T1 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Add n t CKDK (NOM) DK CKDK (MIN DK CKDK (MAX DK# DK ...
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Figure 20: Consecutive WRITE-to-WRITE T0 T1 CK# CK COMMAND WRITE NOP Bank a, ADDRESS Add n DK Notes (or bn) = data-in for bank a (or bank ...
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Figure 21: WRITE-to-READ T0 T1 CK# CK COMMAND WRITE READ Bank a, Bank b, ADDRESS Add n Add n QK# DK# DK QVLD Notes data-in for bank a and address ...
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Figure 22: WRITE – DM Operation T1 T0 CK# CK COMMAND NOP WRITE Bank a, ADDRESS Add n DK Notes data-in from address n. 2. Subsequent elements of burst are provided on following ...
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READ Figure 23: Basic READ Burst Timing T1 T0 CK# CK COMMAND NOP READ Bank a ADDRESS Add CKQK (MIN) QK# QK QVLD Q t CKQK (MAX) QK# QK QVLD Q Notes data-out ...
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Figure 24: Consecutive READ Bursts ( CK# CK COMMAND READ Bank a ADDRESS Add n QVLD QK Notes ( cn) = data-out from bank a (or bank b or bank ...
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Figure 26: READ-to-WRITE T0 T1 CK# CK COMMAND READ WRITE Bank a, Bank b, ADDRESS Add n Add n DM QK QVLD D Q Notes data-out from bank a and address n. ...
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Figure 28: Read Data Valid Window for x18 Device Q (last valid data) Q (first valid data) All Qs and QKs collectively Q (last valid data) Q (first valid data) All Qs and QKs collectively t Notes: 1. QHP is ...
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AUTO REFRESH Figure 29: AUTO REFRESH Cycle COMMAND ADDRESS BANK DK, DK# DM Notes: 1. AREFx = AUTO REFRESH command to bank x. 2. ACx = any command to bank x; ACy = any command to bank y. 3. BAx ...
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On-Die Termination Figure 30: READ Burst with ODT T0 T1 CK# CK COMMAND READ NOP Bank a, ADDRESS Col QK# QK QVLD Q Q ODT QK# QK QVLD Q Q ODT QK# QK QVLD Q Q ...
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Figure 31: READ-NOP-READ with ODT T0 T1 CK# CK COMMAND READ NOP Bank a, ADDRESS Col QK# QK QVLD Q Q ODT Notes (or bn) = data-out from bank a (or bank b) ...
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Multiplexed Address Mode Figure 33: Command Description in Multiplexed Address Mode READ CK# CK CS# WE# REF# ADDRESS Ax Ay BANK BA ADDRESS Notes: 1. The minimum setup and hold times of the two address parts are defined PDF: 09005aef815b2df8/Source: ...
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Figure 34: Power-Up/Initialization Sequence in Multiplexed Address Mode V EXT REF CK CKH t CKL DKH t DKL COMMAND NOP ...
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Figure 35: Mode Register Definition in Multiplexed Address Mode M8 Internal 50Ω 4 (default Notes: 1. Bits A10–A18 must be set to zero not used in MRS not available. ...
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Address Mapping in Multiplexed Address Mode Table 19: Address Mapping in Multiplexed Address Mode Note 1 applies to the entire table Data Burst Width Length Ball A0 x18 ...
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Configuration Tables in Multiplexed Address Mode In multiplexed address mode, the read and write latencies are increased by one clock cycle. However, the RLDRAM cycle time remains the same as when in non-multiplexed address mode. Table 20: Cycle Time and ...
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Figure 37: Consecutive WRITE Bursts with Multiplexed Addressing T0 T1 CK# CK COMMAND WRITE NOP ADDRESS Ax Ay BANK Bank a DK Notes: 1. Data from the second WRITE command to bank a ...
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Figure 38: WRITE-to-READ with Multiplexed Addressing T0 T1 CK# CK COMMAND WRITE NOP ADDRESS BANK Bank a QK# DK# DK QVLD Notes data-in for bank ...
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Figure 39: Consecutive READ Burst with Multiplexed Addressing T0 CK# CK COMMAND READ ADDRESS Ax BANK Bank a QVLD QK Notes data-out from bank a. 2. Nominal conditions are assumed for specifications not defined. ...
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Figure 40: READ-to-WRITE with Multiplexed Addressing T0 T1 CK# CK READ NOP COMMAND ADDRESS Ax Ay Bank a BANK DM QK# QK DK# DK QVLD D Q Notes data-out from bank ...
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IEEE 1149.1 Serial Boundary Scan (JTAG) RLDRAM incorporates a serial boundary-scan test access port (TAP) for the purpose of testing the connectivity of the device once it has been mounted on a printed circuit board (PCB). As the complexity of ...
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Test Data-In (TDI) The TDI ball is used to serially input test instructions and data into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the ...
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Update-DR When the EXTEST instruction is selected, there are latched parallel outputs of the boundary-scan shift register that only change state during the update-DR controller state. Instruction Register States The instruction register states of the TAP controller are similar to ...
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Performing a TAP RESET A reset is performed by forcing TMS HIGH (V RESET does not affect the operation of the RLDRAM and may be performed while the RLDRAM is operating. At power-up, the TAP is reset internally to ensure ...
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TAP Instruction Set Overview Many different instructions (2 combinations used are listed in Table 26 on page 67. These six instructions are described in detail below. The remaining instructions are reserved and should not be used. The TAP controller used ...
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SAMPLE/ PRELOAD instruction. If this is an issue still possible to capture all other signals and simply ignore the value of ...
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Figure 44: TAP Timing Test clock Test mode select Test data-in Test data-out Table 21: TAP Input AC Logic Levels +0°C ≤ T ≤ +95°C; +1.7V ≤ Description Input high (Logic 1) voltage Input low (Logic 0) voltage ...
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Table 23: TAP DC Electrical Characteristics and Operating Conditions +0°C ≤ T ≤ +95°C; +1.7V ≤ Description Input high (logic 1) voltage Input low (logic 0) voltage Input leakage current Output leakage current Output low voltage Output low ...
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Table 26: Instruction Codes Instruction Code Extest 0000 0000 ID code 0010 0001 0000 0101 Sample/preload Clamp 0000 0111 High-Z 0000 0011 Bypass 1111 1111 Table 27: Boundary Scan (Exit) Order Bit# Ball ...
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Table 27: Boundary Scan (Exit) Order (continued) Bit# Ball 32 U11 33 T10 34 T10 35 T11 36 T11 37 R10 38 R10 Notes: 1. Any unused balls in the order will read as a logic “0.” 8000 S. Federal ...